Merge pull request #40 from os-fpga/fail_sim_1.1.3_internal

Fail sim 1.1.3 internal
os-fpga · Apr 5, 2024 · 6583687 · 6583687
2 parents ae485ee + 54fd846
commit 6583687
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Showing 8 changed files with 111 additions and 18 deletions.
diff --git a/blackbox_models/cell_sim_blackbox.v b/blackbox_models/cell_sim_blackbox.v
@@ -268,8 +268,11 @@ module I_BUF_DS #(
   parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
 `endif // RAPIDSILICON_INTERNAL
   ) (
+  (* iopad_external_pin *)
   input logic I_P,
+  (* iopad_external_pin *)
   input logic I_N,
+  (* iopad_external_pin *)
   input logic EN,
   output reg O
 );
@@ -475,7 +478,9 @@ module O_BUF_DS
 `endif // RAPIDSILICON_INTERNAL
   (
   input logic I,
+  (* iopad_external_pin *)
   output logic O_P,
+  (* iopad_external_pin *)
   output logic O_N
 );
 endmodule
@@ -497,7 +502,9 @@ module O_BUFT_DS #(
   ) (
   input logic I,
   input logic T,
+  (* iopad_external_pin *)
   output logic O_P,
+  (* iopad_external_pin *)
   output logic O_N
 );
 endmodule

diff --git a/specs_internal/FIFO18KX2.yaml b/specs_internal/FIFO18KX2.yaml
@@ -180,12 +180,16 @@ parameters:
       desc: FIFO data write width, FIFO 1 (9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 9
+      - 18
     DATA_READ_WIDTH1:
       desc: FIFO data read width, FIFO 1 (9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 9
+      - 18
     FIFO_TYPE1:
       desc: Synchronous or Asynchronous data transfer, FIFO 1 (SYNCHRONOUS/ASYNCHRONOUS)
       default: SYNCHRONOUS
@@ -204,12 +208,16 @@ parameters:
       desc: FIFO data write width, FIFO 2 (9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 9
+      - 18
     DATA_READ_WIDTH2:
       desc: FIFO data read width, FIFO 2 (9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 9
+      - 18
     FIFO_TYPE2:
       desc: Synchronous or Asynchronous data transfer, FIFO 2 (SYNCHRONOUS/ASYNCHRONOUS)
       default: SYNCHRONOUS

diff --git a/specs_internal/FIFO36K.yaml b/specs_internal/FIFO36K.yaml
@@ -117,12 +117,18 @@ parameters:
       desc: FIFO data write width (9, 18, 36)
       type: integer
       default: 36
-      range: 1 .. 36
+      values:
+      - 9
+      - 18
+      - 36
     DATA_READ_WIDTH:
       desc: FIFO data read width (9, 18, 36)
       type: integer
       default: 36
-      range: 1 .. 36
+      values:
+      - 9
+      - 18
+      - 36
     FIFO_TYPE:
       desc: Synchronous or Asynchronous data transfer (SYNCHRONOUS/ASYNCHRONOUS)
       default: SYNCHRONOUS

diff --git a/specs_internal/I_BUF_DS.yaml b/specs_internal/I_BUF_DS.yaml
@@ -51,12 +51,15 @@ ports:
    I_P:
      dir: input
      desc: Data positive input (connect to top-level port)
+     bb_attributes: iopad_external_pin
    I_N:
      dir: input
      desc: Data negative input (connect to top-level port)
+     bb_attributes: iopad_external_pin
    EN:
      dir: input
      desc: Enable the input
+     bb_attributes: iopad_external_pin
    O:
      dir: output
      type: reg

diff --git a/specs_internal/O_BUFT_DS.yaml b/specs_internal/O_BUFT_DS.yaml
@@ -57,9 +57,11 @@ ports:
    O_P:
      dir: output
      desc: Data positive output (connect to top-level port)
+     bb_attributes: iopad_external_pin
    O_N:
      dir: output
      desc: Data negative output (connect to top-level port)
+     bb_attributes: iopad_external_pin
 
 parameters:
    WEAK_KEEPER:

diff --git a/specs_internal/O_BUF_DS.yaml b/specs_internal/O_BUF_DS.yaml
@@ -54,9 +54,11 @@ ports:
    O_P:
      dir: output
      desc: Data positive output (connect to top-level port)
+     bb_attributes: iopad_external_pin
    O_N:
      dir: output
      desc: Data negative output (connect to top-level port)
+     bb_attributes: iopad_external_pin
 
 
 # set in SDC or by synthesis attribute      

diff --git a/specs_internal/TDP_RAM18KX2.yaml b/specs_internal/TDP_RAM18KX2.yaml
@@ -188,22 +188,42 @@ parameters:
       desc: Write data width on port A, RAM 1 (1, 2, 4, 9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
     WRITE_WIDTH_B1:
       desc: Write data width on port B, RAM 1 (1, 2, 4, 9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
     READ_WIDTH_A1:
       desc: Read data width on port A, RAM 1 (1, 2, 4, 9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
     READ_WIDTH_B1:
       desc: Read data width on port B, RAM 1 (1, 2, 4, 9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
     INIT2:
       desc: Initial Contents of memory, RAM 2
       default: "{16384{1'b0}}"
@@ -214,20 +234,41 @@ parameters:
       vector: 2048
     WRITE_WIDTH_A2:
       desc: Write data width on port A, RAM 2 (1, 2, 4, 9, 18)
+      type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
     WRITE_WIDTH_B2:
       desc: Write data width on port B, RAM 2 (1, 2, 4, 9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
     READ_WIDTH_A2:
       desc: Read data width on port A, RAM 2 (1, 2, 4, 9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
     READ_WIDTH_B2:
       desc: Read data width on port B, RAM 2 (1, 2, 4, 9, 18)
       type: integer
       default: 18
-      range: 1 .. 18
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
diff --git a/specs_internal/TDP_RAM36K.yaml b/specs_internal/TDP_RAM36K.yaml
@@ -127,19 +127,43 @@ parameters:
       desc: Write data width on port A (1, 2, 4, 9, 18, 36)
       type: integer
       default: 36
-      range: 1 .. 36
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
+      - 36
     READ_WIDTH_A:
       desc: Read data width on port A (1, 2, 4, 9, 18, 36)
       type: integer
       default: WRITE_WIDTH_A
-      range: 1 .. 36
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
+      - 36
     WRITE_WIDTH_B:
       desc: Write data width on port B (1, 2, 4, 9, 18, 36)
       type: integer
       default: WRITE_WIDTH_A
-      range: 1 .. 36
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
+      - 36
     READ_WIDTH_B:
       desc: Read data width on port B (1, 2, 4, 9, 18, 36)
       type: integer
       default: READ_WIDTH_A
-      range: 1 .. 36
+      values:
+      - 1
+      - 2
+      - 4
+      - 9
+      - 18
+      - 36