Merge pull request #35 from os-fpga/pass_sim_1.1.1_internal

Pulling SIMs release 1.1.1 into main.
os-fpga · Mar 27, 2024 · 9257760 · 9257760
2 parents 7311edd + fa9c0f0
commit 9257760
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Showing 3 changed files with 14 additions and 14 deletions.
diff --git a/sim_models_internal/verilog/FIFO18KX2.v b/sim_models_internal/verilog/FIFO18KX2.v
@@ -8,13 +8,13 @@
 //
 
 module FIFO18KX2 #(
-  parameter DATA_WRITE_WIDTH1 = 18, // FIFO data write width, FIFO 1 (1-18)
-  parameter DATA_READ_WIDTH1 = 18, // FIFO data read width, FIFO 1 (1-18)
+  parameter DATA_WRITE_WIDTH1 = 18, // FIFO data write width, FIFO 1 (9, 18)
+  parameter DATA_READ_WIDTH1 = 18, // FIFO data read width, FIFO 1 (9, 18)
   parameter FIFO_TYPE1 = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer, FIFO 1 (SYNCHRONOUS/ASYNCHRONOUS)
   parameter [10:0] PROG_EMPTY_THRESH1 = 11'h004, // 11-bit Programmable empty depth, FIFO 1
   parameter [10:0] PROG_FULL_THRESH1 = 11'h7fa, // 11-bit Programmable full depth, FIFO 1
-  parameter DATA_WRITE_WIDTH2 = 18, // FIFO data write width, FIFO 2 (1-18)
-  parameter DATA_READ_WIDTH2 = 18, // FIFO data read width, FIFO 2 (1-18)
+  parameter DATA_WRITE_WIDTH2 = 18, // FIFO data write width, FIFO 2 (9, 18)
+  parameter DATA_READ_WIDTH2 = 18, // FIFO data read width, FIFO 2 (9, 18)
   parameter FIFO_TYPE2 = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer, FIFO 2 (SYNCHRONOUS/ASYNCHRONOUS)
   parameter [10:0] PROG_EMPTY_THRESH2 = 11'h004, // 11-bit Programmable empty depth, FIFO 2
   parameter [10:0] PROG_FULL_THRESH2 = 11'h7fa // 11-bit Programmable full depth, FIFO 2

diff --git a/sim_models_internal/verilog/FIFO36K.v b/sim_models_internal/verilog/FIFO36K.v
@@ -8,8 +8,8 @@
 //
 
 module FIFO36K #(
-  parameter DATA_WRITE_WIDTH = 36, // FIFO data write width (1-36)
-  parameter DATA_READ_WIDTH = 36, // FIFO data read width (1-36)
+  parameter DATA_WRITE_WIDTH = 36, // FIFO data write width (9, 18, 36)
+  parameter DATA_READ_WIDTH = 36, // FIFO data read width (9, 18, 36)
   parameter FIFO_TYPE = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer (SYNCHRONOUS/ASYNCHRONOUS)
   parameter [11:0] PROG_EMPTY_THRESH = 12'h004, // 12-bit Programmable empty depth
   parameter [11:0] PROG_FULL_THRESH = 12'hffa // 12-bit Programmable full depth

diff --git a/sim_models_internal/verilog/TDP_RAM36K.v b/sim_models_internal/verilog/TDP_RAM36K.v
@@ -10,10 +10,10 @@
 module TDP_RAM36K #(
   parameter [32767:0] INIT = {32768{1'b0}}, // Initial Contents of memory
   parameter [4095:0] INIT_PARITY = {4096{1'b0}}, // Initial Contents of memory
-  parameter WRITE_WIDTH_A = 36, // Write data width on port A (1-36)
-  parameter READ_WIDTH_A = WRITE_WIDTH_A, // Read data width on port A (1-36)
-  parameter WRITE_WIDTH_B = WRITE_WIDTH_A, // Write data width on port B (1-36)
-  parameter READ_WIDTH_B = READ_WIDTH_A // Read data width on port B (1-36)
+  parameter WRITE_WIDTH_A = 36, // Write data width on port A (1, 2, 4, 9, 18, 36)
+  parameter READ_WIDTH_A = WRITE_WIDTH_A, // Read data width on port A (1, 2, 4, 9, 18, 36)
+  parameter WRITE_WIDTH_B = WRITE_WIDTH_A, // Write data width on port B (1, 2, 4, 9, 18, 36)
+  parameter READ_WIDTH_B = READ_WIDTH_A // Read data width on port B (1, 2, 4, 9, 18, 36)
 ) (
   input WEN_A, // Write-enable port A
   input WEN_B, // Write-enable port B
@@ -263,7 +263,7 @@ module TDP_RAM36K #(
     if (RAM_ADDR_WIDTH == A_WRITE_ADDR_WIDTH)
       find_a_write_index = 0;
     else    
-      find_a_write_index = ADDR_A[15-A_WRITE_ADDR_WIDTH:14-RAM_ADDR_WIDTH]; 
+      find_a_write_index = ADDR_A[14-RAM_ADDR_WIDTH:15-A_WRITE_ADDR_WIDTH];
 
   endfunction
 
@@ -273,7 +273,7 @@ module TDP_RAM36K #(
     if (RAM_ADDR_WIDTH == A_READ_ADDR_WIDTH)
       find_a_read_index = 0;
     else    
-      find_a_read_index = ADDR_A[15-A_READ_ADDR_WIDTH:14-RAM_ADDR_WIDTH]; 
+      find_a_read_index = ADDR_A[14-RAM_ADDR_WIDTH:15-A_READ_ADDR_WIDTH];
 
   endfunction
 
@@ -283,7 +283,7 @@ module TDP_RAM36K #(
     if (RAM_ADDR_WIDTH == B_WRITE_ADDR_WIDTH)
       find_b_write_index = 0;
     else    
-      find_b_write_index = ADDR_B[15-B_WRITE_ADDR_WIDTH:14-RAM_ADDR_WIDTH]; 
+      find_b_write_index = ADDR_B[14-RAM_ADDR_WIDTH:15-B_WRITE_ADDR_WIDTH];
 
   endfunction
 
@@ -293,7 +293,7 @@ module TDP_RAM36K #(
     if (RAM_ADDR_WIDTH == B_READ_ADDR_WIDTH)
       find_b_read_index = 0;
     else    
-      find_b_read_index = ADDR_B[15-B_READ_ADDR_WIDTH:14-RAM_ADDR_WIDTH]; 
+      find_b_read_index = ADDR_B[14-RAM_ADDR_WIDTH:15-B_READ_ADDR_WIDTH];
 
   endfunction