Merge pull request #127 from os-fpga/revert-125-bilal458-patch-1

Revert "Rename DLY_SEL_DCODER.v to DLY_SEL_DECODER.v"
os-fpga · Oct 2, 2024 · c128be0 · c128be0
2 parents de52855 + 14719e0
commit c128be0
Showing 1 changed file with 0 additions and 0 deletions.
diff --git a/sim_models/verilog/DLY_SEL_DECODER.v → sim_models/verilog/DLY_SEL_DCODER.v b/sim_models/verilog/DLY_SEL_DECODER.v → sim_models/verilog/DLY_SEL_DCODER.v