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Merge pull request #140 from os-fpga/pass_sim_1.6.2
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Pulling SIMs release 1.6.2 into main.
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bilal458 authored Nov 27, 2024
2 parents cbd8a65 + 86d68d2 commit c86d557
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17 changes: 17 additions & 0 deletions blackbox_models/cell_sim_blackbox.v
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Expand Up @@ -14,6 +14,23 @@ module BOOT_CLOCK #(
endmodule
`endcelldefine
//
// CARRY_BREAK black box model
// CARRY_BREAK describes an implementation of the regular CARRY module where we break the COUT -> next CIN link
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module CARRY_BREAK (
input logic P,
input logic G,
input logic CIN,
output logic O,
output logic COUT
);
endmodule
`endcelldefine
//
// CARRY black box model
// FLE carry logic
//
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