slight fix

os-fpga · Nov 13, 2023 · 5e1c257 · 5e1c257
1 parent 8c48326
commit 5e1c257
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/rapidsilicon/ip/fifo_generator/v1_0/litex_wrapper/fifo_litex_generator.py b/rapidsilicon/ip/fifo_generator/v1_0/litex_wrapper/fifo_litex_generator.py
@@ -1448,7 +1448,7 @@ def __init__(self, data_width_write, data_width_read, synchronous, full_threshol
                     self.comb += self.sync_rdclk_wrtptr_binary_multiple[0:-1].eq(self.sync_rdclk_wrtptr_binary[0:-1]*(int(data_width_write/(data_width_read if data_width_read >= 36 else 36))))
                     self.comb += self.sync_rdclk_wrtptr_binary_multiple[-1].eq(self.sync_rdclk_wrtptr_binary[-1])
                     self.sync_wrtclk_rdptr_binary_div = Signal(math.ceil(math.log2((data_width_write/data_width_read)*depth)) + 2, reset=0)
-                    self.comb += self.sync_wrtclk_rdptr_binary_div.eq((self.sync_wrtclk_rdptr_binary + int(data_width_write/(data_width_read if data_width_read >= 36 else 36)) - 1) >> (int(data_width_write/(data_width_read if data_width_read >= 36 else 36)) - 1) << (int(data_width_write/(data_width_read if data_width_read >= 36 else 36)) - 1))
+                    self.comb += self.sync_wrtclk_rdptr_binary_div.eq((self.sync_wrtclk_rdptr_binary + decimal_to_binary(int(data_width_write/(data_width_read if data_width_read >= 36 else 36)))) >> (decimal_to_binary(int(data_width_write/(data_width_read if data_width_read >= 36 else 36)))) << (decimal_to_binary(int(data_width_write/(data_width_read if data_width_read >= 36 else 36)))))
                 elif (data_width_write < data_width_read):
                     self.rd_pointer_multiple = Signal(math.ceil(math.log2(depth)) + 2, reset=0)
                     self.comb += self.rd_pointer_multiple[0: -1].eq(self.rd_ptr[0: -1]*int((data_width_read/data_width_write)/clocks_for_output))