Update Makefile

os-fpga · Dec 6, 2024 · 5e292a2 · 5e292a2
1 parent a82ffde
commit 5e292a2
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/rapidsilicon/ip/axi_register/v1_0/sim/Makefile b/rapidsilicon/ip/axi_register/v1_0/sim/Makefile
@@ -48,7 +48,7 @@ FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type d -name "project*" |
 #@echo "The folder name is: $(FOLDER_NAME)"
 
 ifeq ($(POST_SYNTH_SIM), 0)
-	VERILOG_SOURCES += ./../src*.v
+	VERILOG_SOURCES += ./../src/*.v
 else ifeq ($(POST_SYNTH_SIM), 1)
 	VERILOG_SOURCES += $(Raptor_PATH)/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/*.v
 	VERILOG_SOURCES += ./../../../../../../../synth_1_1/synthesis/$(FOLDER_NAME)_post_synth.v