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added i_delay inst design at place
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@zhergarvi
zhergarvi committed Sep 19, 2024
1 parent a716d9d commit 0f39e73
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72 changes: 72 additions & 0 deletions EDA-3249/I_DELAY_primitive_inst/I_DELAY_primitive_inst.ospr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- -->
<!--Copyright (c) 2021-2022 The Open-Source FPGA Foundation.-->
<Project Version="1.2.3">
<Configuration>
<Option Name="ID" Val="20240919133500008"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="Project Type" Val="0"/>
</Configuration>
<CompilerConfig>
<Opt Name="LibPath" Val="./rtl"/>
<Opt Name="IncludePath" Val="./rtl"/>
<Opt Name="LibExt" Val=".v .sv"/>
<Opt Name="Macro" Val=""/>
</CompilerConfig>
<SimulationConfig>
<Opt Name="LibPath" Val=""/>
<Opt Name="IncludePath" Val=""/>
<Opt Name="LibExt" Val=""/>
<Opt Name="Macro" Val=""/>
</SimulationConfig>
<IpConfig>
<Option Name="InstancePaths" Val=""/>
<Option Name="CatalogPaths" Val=""/>
<Option Name="InstanceCmds" Val=""/>
</IpConfig>
<FileSets>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="run_1/I_DELAY_primitive_inst.srcs/constrs_1"/>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="run_1/I_DELAY_primitive_inst.srcs/sim_1">
<Config>
<Option Name="TopModule" Val=""/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="run_1/I_DELAY_primitive_inst.srcs/sources_1">
<File Path="$OSRCDIR/../rtl/I_DELAY_primitive_inst.v"/>
<Group Id="7" Name="unit_0" Files="$OSRCDIR/../rtl/I_DELAY_primitive_inst.v" LibCommand="" LibName=""/>
<Config>
<Option Name="TopModule" Val="I_DELAY_primitive_inst"/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
</FileSets>
<Runs>
<Run Name="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="synth_1"/>
<Run Name="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="">
<Option Name="Compilation Flow" Val="Classic Flow"/>
<Option Name="Device" Val="1VG28"/>
<Option Name="Family" Val="Virgo"/>
<Option Name="LanguageVersion" Val="SYSTEMVERILOG_2005"/>
<Option Name="Package" Val="F484A"/>
<Option Name="Series" Val="Virgo"/>
<Option Name="TargetLanguage" Val="VERILOG"/>
</Run>
</Runs>
<Tasks Version="0.0.0">
<Task ID="0" Status="0" Enable="1"/>
<Task ID="1" Status="2" Enable="1"/>
<Task ID="6" Status="2" Enable="1"/>
<Task ID="10" Status="3" Enable="1"/>
<Task ID="15" Status="0" Enable="1"/>
<Task ID="19" Status="0" Enable="1"/>
<Task ID="20" Status="0" Enable="1"/>
<Task ID="21" Status="0" Enable="0"/>
<Task ID="23" Status="2" Enable="1"/>
<Task ID="28" Status="0" Enable="1"/>
<Task ID="31" Status="0" Enable="1"/>
<Task ID="34" Status="0" Enable="1"/>
<Task ID="37" Status="0" Enable="1"/>
</Tasks>
<Compiler Version="0.0.0" CompilerState="4"/>
</Project>
5 changes: 5 additions & 0 deletions EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd
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read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
verilog_defines
read_verilog -I../../../.././rtl -I../../../../ -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v

analyze -top I_DELAY_primitive_inst
149 changes: 149 additions & 0 deletions EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt
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/*******************************************************************************
Copyright (c) 2022-2024 Rapid Silicon
This source code contains proprietary information belonging to Rapid Silicon
(the "licensor") released under license and non-disclosure agreement to the
recipient (the "licensee").

The information shared and protected by the license and non-disclosure agreement
includes but is not limited to the following:
* operational algorithms of the product
* logos, graphics, source code, and visual presentation of the product
* confidential operational information of the licensor

The recipient of this source code is NOT permitted to publicly disclose,
re-use, archive beyond the period of the license agreement, transfer to a
sub-licensee, or re-implement any portion of the content covered by the license
and non-disclosure agreement without the prior written consent of the licensor.
*********************************************************************************/

Version : 2024.09
Build : 1.2.3
Hash : 89d4d1b
Date : Sep 19 2024
Type : Engineering
Log Time : Thu Sep 19 08:35:00 2024 GMT
/*******************************************************************************
Copyright (c) 2022-2024 Rapid Silicon
This source code contains proprietary information belonging to Rapid Silicon
(the "licensor") released under license and non-disclosure agreement to the
recipient (the "licensee").

The information shared and protected by the license and non-disclosure agreement
includes but is not limited to the following:
* operational algorithms of the product
* logos, graphics, source code, and visual presentation of the product
* confidential operational information of the licensor

The recipient of this source code is NOT permitted to publicly disclose,
re-use, archive beyond the period of the license agreement, transfer to a
sub-licensee, or re-implement any portion of the content covered by the license
and non-disclosure agreement without the prior written consent of the licensor.
*********************************************************************************/

Version : 2024.09
Build : 1.2.3
Hash : 89d4d1b
Date : Sep 19 2024
Type : Engineering
Log Time : Thu Sep 19 08:35:00 2024 GMT

/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <[email protected]> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/

Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os)


-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd' --

1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation.
Generating RTLIL representation for module `\BOOT_CLOCK'.
Generating RTLIL representation for module `\CARRY'.
Generating RTLIL representation for module `\CLK_BUF'.
Generating RTLIL representation for module `\DFFNRE'.
Generating RTLIL representation for module `\DFFRE'.
Generating RTLIL representation for module `\DSP19X2'.
Generating RTLIL representation for module `\DSP38'.
Generating RTLIL representation for module `\FCLK_BUF'.
Generating RTLIL representation for module `\FIFO18KX2'.
Generating RTLIL representation for module `\FIFO36K'.
Generating RTLIL representation for module `\I_BUF_DS'.
Generating RTLIL representation for module `\I_BUF'.
Generating RTLIL representation for module `\I_DDR'.
Generating RTLIL representation for module `\I_DELAY'.
Generating RTLIL representation for module `\I_FAB'.
Generating RTLIL representation for module `\I_SERDES'.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\LUT5'.
Generating RTLIL representation for module `\LUT6'.
Generating RTLIL representation for module `\O_BUF_DS'.
Generating RTLIL representation for module `\O_BUFT_DS'.
Generating RTLIL representation for module `\O_BUFT'.
Generating RTLIL representation for module `\O_BUF'.
Generating RTLIL representation for module `\O_DDR'.
Generating RTLIL representation for module `\O_DELAY'.
Generating RTLIL representation for module `\O_FAB'.
Generating RTLIL representation for module `\O_SERDES_CLK'.
Generating RTLIL representation for module `\O_SERDES'.
Generating RTLIL representation for module `\PLL'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'.
Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'.
Generating RTLIL representation for module `\TDP_RAM18KX2'.
Generating RTLIL representation for module `\TDP_RAM36K'.
Generating RTLIL representation for module `\LATCH'.
Generating RTLIL representation for module `\LATCHN'.
Generating RTLIL representation for module `\LATCHR'.
Generating RTLIL representation for module `\LATCHS'.
Generating RTLIL representation for module `\LATCHNR'.
Generating RTLIL representation for module `\LATCHNS'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v
Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v' to AST representation.
Generating RTLIL representation for module `\I_DELAY_primitive_inst'.
Successfully finished Verilog frontend.

-- Running command `hierarchy -top I_DELAY_primitive_inst' --

3. Executing HIERARCHY pass (managing design hierarchy).

3.1. Analyzing design hierarchy..
Top module: \I_DELAY_primitive_inst

3.2. Analyzing design hierarchy..
Top module: \I_DELAY_primitive_inst
Removed 0 unused modules.

Dumping file hier_info.json ...
Process module "I_DELAY"
Dumping file port_info.json ...

End of script. Logfile hash: 561b84ddef, CPU: user 0.03s system 0.01s, MEM: 15.88 MB peak
Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os)
Time spent: 94% 4x read_verilog (0 sec), 3% 1x analyze (0 sec), ...
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