Update ICB bitstream

os-fpga · Aug 31, 2024 · 1b14e6c · 1b14e6c
1 parent 4937040
commit 1b14e6c
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Showing 65 changed files with 33,183 additions and 28,160 deletions.
diff --git a/icb_bitstream/feedthrough/constraints.sdc b/icb_bitstream/feedthrough/constraints.sdc
@@ -1,6 +1,4 @@
 # pin locations
-set_property mode Mode_BP_SDR_A_RX HP_1_0_0P
 set_pin_loc din HP_1_0_0P
 
-set_property mode Mode_BP_SDR_B_TX HP_1_1_0N
 set_pin_loc dout HP_1_1_0N
diff --git a/icb_bitstream/flop2flop/constraints.sdc b/icb_bitstream/flop2flop/constraints.sdc
@@ -1,12 +1,6 @@
-# Clock
-create_clock -period 5 -name clk
-
 # pin locations
-set_property mode Mode_BP_SDR_A_RX HP_1_CC_10_5P
-set_pin_loc clk HP_1_CC_10_5P
+set_pin_loc clk HP_1_CC_18_9P
 
-set_property mode Mode_BP_SDR_A_RX HP_1_0_0P
 set_pin_loc din HP_1_0_0P
 
-set_property mode Mode_BP_SDR_B_TX HP_1_1_0N
 set_pin_loc dout HP_1_1_0N
diff --git a/icb_bitstream/golden/feedthrough/config.json b/icb_bitstream/golden/feedthrough/config.json
diff --git a/icb_bitstream/golden/feedthrough/design_edit.sdc b/icb_bitstream/golden/feedthrough/design_edit.sdc
@@ -0,0 +1,45 @@
+#############
+#
+# Fabric clock assignment
+#
+#############
+
+#############
+#
+# Each pin mode and location assignment
+#
+#############
+# Pin      din              :: I_BUF
+# set_mode MODE_BP_DIR_A_RX HP_1_0_0P
+# set_io   din              HP_1_0_0P --> (original)
+set_io     $ibuf_din        HP_1_0_0P -mode          MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A
+
+# Pin      dout             :: O_BUFT
+# set_mode MODE_BP_DIR_B_TX HP_1_1_0N
+# set_io   dout             HP_1_1_0N --> (original)
+set_io     $auto_396        HP_1_0_0P -mode          MODE_BP_DIR_B_TX -internal_pin f2g_tx_out[5]_A
+
+#############
+#
+# Internal Control Signals
+#
+#############
+# Module: I_BUF
+# LinkedObject: din
+# Location: HP_1_0_0P
+# Port: EN
+# Signal: in:f2g_in_en_{A|B}
+set_io $auto_394 HP_1_0_0P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A
+
+# Module: O_BUFT
+# LinkedObject: dout
+# Location: HP_1_1_0N
+# Port: T
+# Signal: in:f2g_tx_oe_{A|B}
+set_io $auto_395 HP_1_1_0N -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_oe_B
+
+#############
+#
+# Each gearbox core clock
+#
+#############
diff --git a/.../golden/io_buf_ds/io_bitstream.detail.txt → ...olden/feedthrough/io_bitstream.detail.bit b/.../golden/io_buf_ds/io_bitstream.detail.txt → ...olden/feedthrough/io_bitstream.detail.bit
diff --git a/icb_bitstream/golden/feedthrough/io_config.json b/icb_bitstream/golden/feedthrough/io_config.json
@@ -0,0 +1,136 @@
+{
+  "messages" : [
+    "Start of IO Analysis",
+    "  Get Ports",
+    "    Detect input port \\din (index=0, width=1, offset=0)",
+    "    Detect output port \\dout (index=0, width=1, offset=0)",
+    "  Get Port/Standalone Primitives",
+    "    Get important connection of cell \\I_BUF $ibuf$top.$ibuf_din",
+    "      Cell port \\I is connected to input port \\din",
+    "        Parameter \\WEAK_KEEPER: \"NONE\"",
+    "        Data Width: -2",
+    "    Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout",
+    "      Cell port \\O is connected to output port \\dout",
+    "        Data Width: -2",
+    "  Trace \\I_BUF --> \\CLK_BUF",
+    "  Trace \\I_BUF_DS --> \\CLK_BUF",
+    "  Trace \\CLK_BUF --> \\PLL",
+    "  Trace \\BOOT_CLOCK --> \\PLL",
+    "  Trace \\I_BUF --> \\I_DELAY",
+    "  Trace \\I_BUF --> \\I_DDR",
+    "  Trace \\I_BUF --> \\I_SERDES",
+    "  Trace \\I_BUF_DS --> \\I_DELAY",
+    "  Trace \\I_BUF_DS --> \\I_DDR",
+    "  Trace \\I_BUF_DS --> \\I_SERDES",
+    "  Trace \\I_DELAY --> \\I_DDR",
+    "  Trace \\I_DELAY --> \\I_SERDES",
+    "  Trace \\O_BUF --> \\O_DELAY",
+    "  Trace \\O_BUF --> \\O_DDR",
+    "  Trace \\O_BUF --> \\O_SERDES",
+    "  Trace \\O_BUFT --> \\O_DELAY",
+    "  Trace \\O_BUFT --> \\O_DDR",
+    "  Trace \\O_BUFT --> \\O_SERDES",
+    "  Trace \\O_BUF_DS --> \\O_DELAY",
+    "  Trace \\O_BUF_DS --> \\O_DDR",
+    "  Trace \\O_BUF_DS --> \\O_SERDES",
+    "  Trace \\O_BUFT_DS --> \\O_DELAY",
+    "  Trace \\O_BUFT_DS --> \\O_DDR",
+    "  Trace \\O_BUFT_DS --> \\O_SERDES",
+    "  Trace \\O_DELAY --> \\O_DDR",
+    "  Trace \\O_DELAY --> \\O_SERDES",
+    "  Trace \\O_BUF --> \\O_SERDES_CLK",
+    "  Trace \\O_BUFT --> \\O_SERDES_CLK",
+    "  Trace \\O_BUF_DS --> \\O_SERDES_CLK",
+    "  Trace \\O_BUFT_DS --> \\O_SERDES_CLK",
+    "  Trace fabric clock buffer",
+    "  Trace gearbox fast clock source",
+    "  Trace Core/Fabric Clock",
+    "  Double check Core/Fabric Clock",
+    "  Summary",
+    "        |-----------------------------------------------------|",
+    "        |     ******************************************      |",
+    "    IN  | din * I_BUF                                  *      |",
+    "    OUT |     *                                 O_BUFT * dout |",
+    "        |     ******************************************      |",
+    "        |-----------------------------------------------------|",
+    "  Final checking is good",
+    "  Assign location HP_1_0_0P (and properties) to Port din",
+    "  Assign location HP_1_1_0N (and properties) to Port dout",
+    "  Cross-check instances vs wrapped-instances",
+    "  Generate SDC",
+    "    Determine data signals",
+    "      Pin object=din, location: HP_1_0_0P",
+    "        Data signal from object din",
+    "          Module=I_BUF Linked-object=din Port=O Net=$ibuf_din - Found",
+    "      Pin object=dout, location: HP_1_1_0N",
+    "        Data signal from object dout",
+    "          Module=O_BUFT Linked-object=dout Port=I Net=$auto_396 - Found",
+    "    Determine internal control signals",
+    "      Module=I_BUF LinkedObject=din Location=HP_1_0_0P Port=EN Signal=in:f2g_in_en_{A|B}",
+    "      Module=O_BUFT LinkedObject=dout Location=HP_1_1_0N Port=T Signal=in:f2g_tx_oe_{A|B}",
+    "End of IO Analysis"
+  ],
+  "instances" : [
+    {
+      "module" : "I_BUF",
+      "name" : "$ibuf$top.$ibuf_din",
+      "location_object" : "din",
+      "location" : "HP_1_0_0P",
+      "linked_object" : "din",
+      "linked_objects" : {
+        "din" : {
+          "location" : "HP_1_0_0P",
+          "properties" : {
+          }
+        }
+      },
+      "connectivity" : {
+        "I" : "din",
+        "O" : "$ibuf_din"
+      },
+      "parameters" : {
+        "WEAK_KEEPER" : "NONE"
+      },
+      "flags" : [
+        "I_BUF"
+      ],
+      "pre_primitive" : "",
+      "post_primitives" : [
+      ],
+      "route_clock_to" : {
+      },
+      "errors" : [
+      ]
+    },
+    {
+      "module" : "O_BUFT",
+      "name" : "$obuf$top.$obuf_dout",
+      "location_object" : "dout",
+      "location" : "HP_1_1_0N",
+      "linked_object" : "dout",
+      "linked_objects" : {
+        "dout" : {
+          "location" : "HP_1_1_0N",
+          "properties" : {
+          }
+        }
+      },
+      "connectivity" : {
+        "I" : "$ibuf_din",
+        "O" : "dout"
+      },
+      "parameters" : {
+      },
+      "flags" : [
+        "O_BUFT"
+      ],
+      "pre_primitive" : "",
+      "post_primitives" : [
+      ],
+      "route_clock_to" : {
+      },
+      "errors" : [
+      ]
+    }
+  ]
+}