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@chungshien-chai
chungshien-chai committed Sep 9, 2024
2 parents 02f4656 + 77f2dd5 commit 2d55189
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Showing 187 changed files with 933,388 additions and 13 deletions.
20 changes: 10 additions & 10 deletions EDA-3166/rtl/aes_192.v
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Expand Up @@ -19,8 +19,8 @@ module aes_192 (clk, state, key, out);
input [127:0] state;
input [191:0] key;
output [127:0] out;
reg [127:0] s0;
reg [191:0] k0;
reg [127:0] s0=0;
reg [191:0] k0=0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
wire [191:0] k1, k2, k3, k4, k5, k6, k7, k8, k9, k10, k11;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b, k10b, k11b;
Expand Down Expand Up @@ -66,11 +66,11 @@ module expand_key_type_A_192 (clk, in, rcon, out_1, out_2);
input clk;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output reg [191:0] out_1=0;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
reg [31:0] k0a=0, k1a=0, k2a=0, k3a=0, k4a=0, k5a=0;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;

assign {k0, k1, k2, k3, k4, k5} = in;
Expand Down Expand Up @@ -102,11 +102,11 @@ endmodule
module expand_key_type_B_192 (clk, in, out_1, out_2);
input clk;
input [191:0] in;
output reg [191:0] out_1;
output reg [191:0] out_1=0;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v2, v3, v4, v5;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
reg [31:0] k0a=0, k1a=0, k2a=0, k3a=0, k4a=0, k5a=0;

assign {k0, k1, k2, k3, k4, k5} = in;

Expand All @@ -129,11 +129,11 @@ module expand_key_type_C_192 (clk, in, rcon, out_1, out_2);
input clk;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output reg [191:0] out_1=0;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v4, v5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
reg [31:0] k0a=0, k1a=0, k2a=0, k3a=0, k4a=0, k5a=0;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;

assign {k0, k1, k2, k3, k4, k5} = in;
Expand Down Expand Up @@ -164,11 +164,11 @@ module expand_key_type_D_192 (clk, in, rcon, out_1, out_2);
input clk;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output reg [191:0] out_1=0;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
reg [31:0] k0a=0, k1a=0, k2a=0, k3a=0, k4a=0, k5a=0;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;

assign {k0, k1, k2, k3, k4, k5} = in;
Expand Down
2 changes: 1 addition & 1 deletion EDA-3166/rtl/round.v
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
module one_round (clk, state_in, key, state_out);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
output reg [127:0] state_out=0;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
Expand Down
4 changes: 2 additions & 2 deletions EDA-3166/rtl/table.v
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ endmodule
module S (clk, in, out);
input clk;
input [7:0] in;
output reg [7:0] out;
output reg [7:0] out=0;

always @ (posedge clk)
case (in)
Expand Down Expand Up @@ -326,7 +326,7 @@ endmodule
module xS (clk, in, out);
input clk;
input [7:0] in;
output reg [7:0] out;
output reg [7:0] out=0;

always @ (posedge clk)
case (in)
Expand Down
76 changes: 76 additions & 0 deletions EDA-3183/adder_tree/adder_tree.ospr
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@@ -0,0 +1,76 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- -->
<!--Copyright (c) 2021-2022 The Open-Source FPGA Foundation.-->
<Project Version="1.1.55">
<Configuration>
<Option Name="ID" Val="20240902173724514"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="Project Type" Val="0"/>
</Configuration>
<CompilerConfig>
<Opt Name="LibPath" Val="./rtl"/>
<Opt Name="IncludePath" Val="./rtl"/>
<Opt Name="LibExt" Val=".v .sv"/>
<Opt Name="Macro" Val=""/>
</CompilerConfig>
<SimulationConfig>
<Opt Name="LibPath" Val=""/>
<Opt Name="IncludePath" Val=""/>
<Opt Name="LibExt" Val=""/>
<Opt Name="Macro" Val=""/>
</SimulationConfig>
<IpConfig>
<Option Name="InstancePaths" Val=""/>
<Option Name="CatalogPaths" Val=""/>
<Option Name="InstanceCmds" Val=""/>
</IpConfig>
<FileSets>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="run_1/adder_tree.srcs/constrs_1"/>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="run_1/adder_tree.srcs/sim_1">
<File Path="$OSRCDIR/../sim/co_sim_tb/co_sim_adder_tree.v"/>
<File Path="$OSRCDIR/../rtl/adder_tree.sv"/>
<Group Id="11" Name="unit_0" Files="$OSRCDIR/../sim/co_sim_tb/co_sim_adder_tree.v" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_1" Files="$OSRCDIR/../rtl/adder_tree.sv" LibCommand="" LibName=""/>
<Config>
<Option Name="TopModule" Val="co_sim_adder_tree"/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="run_1/adder_tree.srcs/sources_1">
<File Path="$OSRCDIR/../rtl/adder_tree.sv"/>
<Group Id="12" Name="unit_0" Files="$OSRCDIR/../rtl/adder_tree.sv" LibCommand="" LibName=""/>
<Config>
<Option Name="TopModule" Val="adder_tree"/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
</FileSets>
<Runs>
<Run Name="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="synth_1"/>
<Run Name="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="">
<Option Name="Compilation Flow" Val="Classic Flow"/>
<Option Name="Device" Val="1VG28"/>
<Option Name="Family" Val="Virgo"/>
<Option Name="LanguageVersion" Val="SYSTEMVERILOG_2005"/>
<Option Name="Package" Val="F484A"/>
<Option Name="Series" Val="Virgo"/>
<Option Name="TargetLanguage" Val="VERILOG"/>
</Run>
</Runs>
<Tasks Version="0.0.0">
<Task ID="0" Status="0" Enable="1"/>
<Task ID="1" Status="2" Enable="1"/>
<Task ID="6" Status="0" Enable="1"/>
<Task ID="10" Status="0" Enable="1"/>
<Task ID="15" Status="0" Enable="1"/>
<Task ID="19" Status="0" Enable="1"/>
<Task ID="20" Status="0" Enable="1"/>
<Task ID="21" Status="0" Enable="0"/>
<Task ID="23" Status="2" Enable="1"/>
<Task ID="28" Status="0" Enable="1"/>
<Task ID="31" Status="3" Enable="1"/>
<Task ID="34" Status="0" Enable="1"/>
<Task ID="37" Status="0" Enable="1"/>
</Tasks>
<Compiler Version="0.0.0" CompilerState="3"/>
</Project>
5 changes: 5 additions & 0 deletions EDA-3183/adder_tree/run_1/synth_1_1/analysis/adder_tree_analyzer.cmd
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@@ -0,0 +1,5 @@
read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/08_31_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
plugin -i systemverilog
read_systemverilog -synth -top adder_tree -y ../../../.././rtl -I../../../.././rtl -I../../../../ -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/adder_tree/jira/./rtl +libext+.v+.sv -sv /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/adder_tree/jira/./rtl/adder_tree.sv \

analyze -top adder_tree
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