Merge pull request #274 from os-fpga/partial_support_EDA-1435

Partially support RAM inference for this case

EDA-1435/raptor.tcl

@@ -1,16 +1,29 @@
 create_design asym_ram_tdp_write_first_dc
-target_device GEMINI_COMPACT_82x68
+target_device GEMINI_COMPACT_10x8
 add_include_path ./rtl
 add_library_path ./rtl
 add_library_ext .v .sv
 add_design_file ./rtl/asym_ram_tdp_write_first_dc.v
 set_top_module asym_ram_tdp_write_first_dc
+
+# The surelog parser converts blocking to non-blocking,
+# Enabling RAM inference
+parser_type surelog
+
 analyze
+
 synthesize delay
+
+setup_lec_sim
+
+simulate icarus gate 
+
 packing
-global_placement
 place
 route
+
+simulate icarus pnr
+
 sta
 power
 bitstream 

EDA-1435/rtl/asym_ram_tdp_write_first_dc.v

@@ -51,6 +51,9 @@ localparam log2RATIO = log2(RATIO);
 reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
 reg [WIDTHA-1:0] readA;
 reg [WIDTHB-1:0] readB;
+
+// RAM Inference for blocking assignments can be achieved 
+// in this case as it meets the blocking->nonblocking conversion criteria    
 always @(posedge clkB)
 begin
     if (enaB) 
@@ -61,6 +64,8 @@ begin
     end
 end
 
+// This block prevents current mapping in our architecture
+   /*
 always @(posedge clkA)
 begin : portA
 integer i;
@@ -76,6 +81,7 @@ reg [log2RATIO-1:0] lsbaddr ;
             end
     end
 end
+*/
 
 assign doA = readA;
 assign doB = readB;