added auto tb sv testcase

EDA-3183/adder_tree/adder_tree.ospr

@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--                                                   -->
+<!--Copyright (c) 2021-2022 The Open-Source FPGA Foundation.-->
+<Project Version="1.1.55">
+    <Configuration>
+        <Option Name="ID" Val="20240902173724514"/>
+        <Option Name="ActiveSimSet" Val="sim_1"/>
+        <Option Name="Project Type" Val="0"/>
+    </Configuration>
+    <CompilerConfig>
+        <Opt Name="LibPath" Val="./rtl"/>
+        <Opt Name="IncludePath" Val="./rtl"/>
+        <Opt Name="LibExt" Val=".v .sv"/>
+        <Opt Name="Macro" Val=""/>
+    </CompilerConfig>
+    <SimulationConfig>
+        <Opt Name="LibPath" Val=""/>
+        <Opt Name="IncludePath" Val=""/>
+        <Opt Name="LibExt" Val=""/>
+        <Opt Name="Macro" Val=""/>
+    </SimulationConfig>
+    <IpConfig>
+        <Option Name="InstancePaths" Val=""/>
+        <Option Name="CatalogPaths" Val=""/>
+        <Option Name="InstanceCmds" Val=""/>
+    </IpConfig>
+    <FileSets>
+        <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="run_1/adder_tree.srcs/constrs_1"/>
+        <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="run_1/adder_tree.srcs/sim_1">
+            <File Path="$OSRCDIR/../sim/co_sim_tb/co_sim_adder_tree.v"/>
+            <File Path="$OSRCDIR/../rtl/adder_tree.sv"/>
+            <Group Id="11" Name="unit_0" Files="$OSRCDIR/../sim/co_sim_tb/co_sim_adder_tree.v" LibCommand="" LibName=""/>
+            <Group Id="12" Name="unit_1" Files="$OSRCDIR/../rtl/adder_tree.sv" LibCommand="" LibName=""/>
+            <Config>
+                <Option Name="TopModule" Val="co_sim_adder_tree"/>
+                <Option Name="TopModuleLib" Val=""/>
+            </Config>
+        </FileSet>
+        <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="run_1/adder_tree.srcs/sources_1">
+            <File Path="$OSRCDIR/../rtl/adder_tree.sv"/>
+            <Group Id="12" Name="unit_0" Files="$OSRCDIR/../rtl/adder_tree.sv" LibCommand="" LibName=""/>
+            <Config>
+                <Option Name="TopModule" Val="adder_tree"/>
+                <Option Name="TopModuleLib" Val=""/>
+            </Config>
+        </FileSet>
+    </FileSets>
+    <Runs>
+        <Run Name="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="synth_1"/>
+        <Run Name="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="">
+            <Option Name="Compilation Flow" Val="Classic Flow"/>
+            <Option Name="Device" Val="1VG28"/>
+            <Option Name="Family" Val="Virgo"/>
+            <Option Name="LanguageVersion" Val="SYSTEMVERILOG_2005"/>
+            <Option Name="Package" Val="F484A"/>
+            <Option Name="Series" Val="Virgo"/>
+            <Option Name="TargetLanguage" Val="VERILOG"/>
+        </Run>
+    </Runs>
+    <Tasks Version="0.0.0">
+        <Task ID="0" Status="0" Enable="1"/>
+        <Task ID="1" Status="2" Enable="1"/>
+        <Task ID="6" Status="0" Enable="1"/>
+        <Task ID="10" Status="0" Enable="1"/>
+        <Task ID="15" Status="0" Enable="1"/>
+        <Task ID="19" Status="0" Enable="1"/>
+        <Task ID="20" Status="0" Enable="1"/>
+        <Task ID="21" Status="0" Enable="0"/>
+        <Task ID="23" Status="2" Enable="1"/>
+        <Task ID="28" Status="0" Enable="1"/>
+        <Task ID="31" Status="3" Enable="1"/>
+        <Task ID="34" Status="0" Enable="1"/>
+        <Task ID="37" Status="0" Enable="1"/>
+    </Tasks>
+    <Compiler Version="0.0.0" CompilerState="3"/>
+</Project>

EDA-3183/adder_tree/run_1/synth_1_1/analysis/adder_tree_analyzer.cmd

@@ -0,0 +1,5 @@
+read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/08_31_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+plugin -i systemverilog
+read_systemverilog -synth  -top adder_tree -y ../../../.././rtl -I../../../.././rtl -I../../../../ -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/adder_tree/jira/./rtl +libext+.v+.sv -sv /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/adder_tree/jira/./rtl/adder_tree.sv \
+
+analyze -top adder_tree