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added random design with post synth sim fail (#267)
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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| create_design design197_15_15_top | ||
| target_device 1VG28 | ||
| add_include_path ./rtl | ||
| add_library_path ./rtl | ||
| add_library_ext .v .sv | ||
| add_design_file ./rtl/design197_15_15_top.v | ||
| set_top_module design197_15_15_top | ||
| analyze | ||
| synthesize delay | ||
| setup_lec_sim | ||
| simulation_options compilation icarus gate | ||
| simulate gate icarus | ||
| packing | ||
| place | ||
| route | ||
| simulation_options compilation icarus pnr | ||
| simulate pnr icarus | ||
| sta | ||
| power | ||
| bitstream |
76 changes: 76 additions & 0 deletions
76
EDA-3226/results_dir/design197_15_15_top/design197_15_15_top.ospr
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|---|---|---|
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- --> | ||
| <!--Copyright (c) 2021-2022 The Open-Source FPGA Foundation.--> | ||
| <Project Version="1.1.64"> | ||
| <Configuration> | ||
| <Option Name="ID" Val="20240912155522888"/> | ||
| <Option Name="ActiveSimSet" Val="sim_1"/> | ||
| <Option Name="Project Type" Val="0"/> | ||
| </Configuration> | ||
| <CompilerConfig> | ||
| <Opt Name="LibPath" Val=".././rtl"/> | ||
| <Opt Name="IncludePath" Val=".././rtl"/> | ||
| <Opt Name="LibExt" Val=".v .sv"/> | ||
| <Opt Name="Macro" Val=""/> | ||
| </CompilerConfig> | ||
| <SimulationConfig> | ||
| <Opt Name="LibPath" Val=""/> | ||
| <Opt Name="IncludePath" Val=""/> | ||
| <Opt Name="LibExt" Val=""/> | ||
| <Opt Name="Macro" Val=""/> | ||
| </SimulationConfig> | ||
| <IpConfig> | ||
| <Option Name="InstancePaths" Val=""/> | ||
| <Option Name="CatalogPaths" Val=""/> | ||
| <Option Name="InstanceCmds" Val=""/> | ||
| </IpConfig> | ||
| <FileSets> | ||
| <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="run_1/design197_15_15_top.srcs/constrs_1"/> | ||
| <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="run_1/design197_15_15_top.srcs/sim_1"> | ||
| <File Path="$OSRCDIR/../sim/co_sim_tb/co_sim_design197_15_15_top.v"/> | ||
| <File Path="$OSRCDIR/../../rtl/design197_15_15_top.v"/> | ||
| <Group Id="11" Name="unit_0" Files="$OSRCDIR/../sim/co_sim_tb/co_sim_design197_15_15_top.v" LibCommand="" LibName=""/> | ||
| <Group Id="11" Name="unit_1" Files="$OSRCDIR/../../rtl/design197_15_15_top.v" LibCommand="" LibName=""/> | ||
| <Config> | ||
| <Option Name="TopModule" Val="co_sim_design197_15_15_top"/> | ||
| <Option Name="TopModuleLib" Val=""/> | ||
| </Config> | ||
| </FileSet> | ||
| <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="run_1/design197_15_15_top.srcs/sources_1"> | ||
| <File Path="$OSRCDIR/../../rtl/design197_15_15_top.v"/> | ||
| <Group Id="7" Name="unit_0" Files="$OSRCDIR/../../rtl/design197_15_15_top.v" LibCommand="" LibName=""/> | ||
| <Config> | ||
| <Option Name="TopModule" Val="design197_15_15_top"/> | ||
| <Option Name="TopModuleLib" Val=""/> | ||
| </Config> | ||
| </FileSet> | ||
| </FileSets> | ||
| <Runs> | ||
| <Run Name="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="synth_1"/> | ||
| <Run Name="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun=""> | ||
| <Option Name="Compilation Flow" Val="Classic Flow"/> | ||
| <Option Name="Device" Val="1VG28"/> | ||
| <Option Name="Family" Val="Virgo"/> | ||
| <Option Name="LanguageVersion" Val="SYSTEMVERILOG_2005"/> | ||
| <Option Name="Package" Val="F484A"/> | ||
| <Option Name="Series" Val="Virgo"/> | ||
| <Option Name="TargetLanguage" Val="VERILOG"/> | ||
| </Run> | ||
| </Runs> | ||
| <Tasks Version="0.0.0"> | ||
| <Task ID="0" Status="0" Enable="1"/> | ||
| <Task ID="1" Status="2" Enable="1"/> | ||
| <Task ID="6" Status="0" Enable="1"/> | ||
| <Task ID="10" Status="0" Enable="1"/> | ||
| <Task ID="15" Status="0" Enable="1"/> | ||
| <Task ID="19" Status="0" Enable="1"/> | ||
| <Task ID="20" Status="0" Enable="1"/> | ||
| <Task ID="21" Status="0" Enable="0"/> | ||
| <Task ID="23" Status="2" Enable="1"/> | ||
| <Task ID="28" Status="0" Enable="1"/> | ||
| <Task ID="31" Status="3" Enable="1"/> | ||
| <Task ID="34" Status="0" Enable="1"/> | ||
| <Task ID="37" Status="0" Enable="1"/> | ||
| </Tasks> | ||
| <Compiler Version="0.0.0" CompilerState="3"/> | ||
| </Project> |
1,346 changes: 1,346 additions & 0 deletions
1,346
EDA-3226/results_dir/design197_15_15_top/run_1/synth_1_1/analysis/analysis.rpt
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17 changes: 17 additions & 0 deletions
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...results_dir/design197_15_15_top/run_1/synth_1_1/analysis/design197_15_15_top_analyzer.cmd
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|---|---|---|
| @@ -0,0 +1,17 @@ | ||
| read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/09_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v | ||
| verilog_defines | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/paritygenerator_top.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/encoder.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/full_adder_top.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/memory_cntrl.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/large_adder.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/shift_reg_top.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/d_latch_top.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/invertion.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/large_mux.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/decoder_top.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/register.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl ../../../../.././rtl/mod_n_counter.v | ||
| read_verilog -I../../../../.././rtl -I../../../../.. -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/verilog_random_designs/design197_15_15_top/results_dir/.././rtl/design197_15_15_top.v | ||
|
|
||
| analyze -top design197_15_15_top |
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