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added EDA-3164 #255

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Aug 27, 2024
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added EDA-3164 #255

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38 changes: 38 additions & 0 deletions EDA-3164/GJC48.v
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module GJC48 (
input wire clk,
input wire reset_n,
input wire [3:0] dma_req_in,
output reg [3:0] dma_ack_out
);

reg [3:0] dma_req_reg;
reg [3:0] dma_ack_reg;

// Instantiate the DMA module
SOC_FPGA_INTF_DMA dma_inst (
.DMA_REQ (dma_req_reg),
.DMA_ACK (dma_ack_reg),
.DMA_CLK (clk),
.DMA_RST_N (reset_n)
);

// Input registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
dma_req_reg <= 4'b0;
end else begin
dma_req_reg <= dma_req_in;
end
end

// Connect output register to top-level output
// Input registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
dma_ack_out <= 4'b0;
end else begin
dma_ack_out <= dma_ack_reg;
end
end

endmodule
77 changes: 77 additions & 0 deletions EDA-3164/GJC48/GJC48.ospr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- -->
<!--Copyright (c) 2021-2022 The Open-Source FPGA Foundation.-->
<Project Version="1.1.51">
<Configuration>
<Option Name="ID" Val="20240827125524110"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="Project Type" Val="0"/>
</Configuration>
<CompilerConfig>
<Opt Name="LibPath" Val=""/>
<Opt Name="IncludePath" Val=""/>
<Opt Name="LibExt" Val=""/>
<Opt Name="Macro" Val=""/>
</CompilerConfig>
<SimulationConfig>
<Opt Name="LibPath" Val=""/>
<Opt Name="IncludePath" Val=""/>
<Opt Name="LibExt" Val=""/>
<Opt Name="Macro" Val=""/>
</SimulationConfig>
<IpConfig>
<Option Name="InstancePaths" Val=""/>
<Option Name="CatalogPaths" Val=""/>
<Option Name="InstanceCmds" Val=""/>
</IpConfig>
<FileSets>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="run_1/GJC48.srcs/constrs_1">
<File Path="$OSRCDIR/../constraints.sdc"/>
<File Path="$OSRCDIR/../pin_constraints.pin"/>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="run_1/GJC48.srcs/sim_1">
<File Path="$OSRCDIR/../co_sim_GJC48.v"/>
<Group Id="7" Name="" Files="$OSRCDIR/../co_sim_GJC48.v" LibCommand="" LibName=""/>
<Config>
<Option Name="TopModule" Val="co_sim_GJC48"/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="run_1/GJC48.srcs/sources_1">
<File Path="$OSRCDIR/../GJC48.v"/>
<Group Id="7" Name="" Files="$OSRCDIR/../GJC48.v" LibCommand="" LibName=""/>
<Config>
<Option Name="TopModule" Val="GJC48"/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
</FileSets>
<Runs>
<Run Name="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="synth_1"/>
<Run Name="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="">
<Option Name="Compilation Flow" Val="Classic Flow"/>
<Option Name="Device" Val="1VG28"/>
<Option Name="Family" Val="Virgo"/>
<Option Name="LanguageVersion" Val="SYSTEMVERILOG_2005"/>
<Option Name="Package" Val="F484A"/>
<Option Name="Series" Val="Virgo"/>
<Option Name="TargetLanguage" Val="VERILOG"/>
</Run>
</Runs>
<Tasks Version="0.0.0">
<Task ID="0" Status="2" Enable="1"/>
<Task ID="1" Status="2" Enable="1"/>
<Task ID="6" Status="0" Enable="1"/>
<Task ID="10" Status="0" Enable="1"/>
<Task ID="15" Status="0" Enable="1"/>
<Task ID="19" Status="0" Enable="1"/>
<Task ID="20" Status="0" Enable="1"/>
<Task ID="21" Status="0" Enable="0"/>
<Task ID="23" Status="2" Enable="1"/>
<Task ID="28" Status="0" Enable="0"/>
<Task ID="31" Status="3" Enable="1"/>
<Task ID="34" Status="0" Enable="1"/>
<Task ID="37" Status="0" Enable="1"/>
</Tasks>
<Compiler Version="0.0.0" CompilerState="3"/>
</Project>
5 changes: 5 additions & 0 deletions EDA-3164/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd
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read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
verilog_defines
read_verilog -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v

analyze -top GJC48
125 changes: 125 additions & 0 deletions EDA-3164/GJC48/run_1/synth_1_1/analysis/analysis.rpt
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/*******************************************************************************
Copyright (c) 2022-2024 Rapid Silicon
This source code contains proprietary information belonging to Rapid Silicon
(the "licensor") released under license and non-disclosure agreement to the
recipient (the "licensee").

The information shared and protected by the license and non-disclosure agreement
includes but is not limited to the following:
* operational algorithms of the product
* logos, graphics, source code, and visual presentation of the product
* confidential operational information of the licensor

The recipient of this source code is NOT permitted to publicly disclose,
re-use, archive beyond the period of the license agreement, transfer to a
sub-licensee, or re-implement any portion of the content covered by the license
and non-disclosure agreement without the prior written consent of the licensor.
*********************************************************************************/

Version : 2024.08
Build : 1.1.51
Hash : c3b8064
Date : Aug 27 2024
Type : Engineering
Log Time : Tue Aug 27 07:56:02 2024 GMT

/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <[email protected]> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/

Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os)


-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd' --

1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation.
Generating RTLIL representation for module `\BOOT_CLOCK'.
Generating RTLIL representation for module `\CARRY'.
Generating RTLIL representation for module `\CLK_BUF'.
Generating RTLIL representation for module `\DFFNRE'.
Generating RTLIL representation for module `\DFFRE'.
Generating RTLIL representation for module `\DSP19X2'.
Generating RTLIL representation for module `\DSP38'.
Generating RTLIL representation for module `\FCLK_BUF'.
Generating RTLIL representation for module `\FIFO18KX2'.
Generating RTLIL representation for module `\FIFO36K'.
Generating RTLIL representation for module `\I_BUF_DS'.
Generating RTLIL representation for module `\I_BUF'.
Generating RTLIL representation for module `\I_DDR'.
Generating RTLIL representation for module `\I_DELAY'.
Generating RTLIL representation for module `\I_FAB'.
Generating RTLIL representation for module `\I_SERDES'.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\LUT5'.
Generating RTLIL representation for module `\LUT6'.
Generating RTLIL representation for module `\O_BUF_DS'.
Generating RTLIL representation for module `\O_BUFT_DS'.
Generating RTLIL representation for module `\O_BUFT'.
Generating RTLIL representation for module `\O_BUF'.
Generating RTLIL representation for module `\O_DDR'.
Generating RTLIL representation for module `\O_DELAY'.
Generating RTLIL representation for module `\O_FAB'.
Generating RTLIL representation for module `\O_SERDES_CLK'.
Generating RTLIL representation for module `\O_SERDES'.
Generating RTLIL representation for module `\PLL'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'.
Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'.
Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'.
Generating RTLIL representation for module `\TDP_RAM18KX2'.
Generating RTLIL representation for module `\TDP_RAM36K'.
Generating RTLIL representation for module `\LATCH'.
Generating RTLIL representation for module `\LATCHN'.
Generating RTLIL representation for module `\LATCHR'.
Generating RTLIL representation for module `\LATCHS'.
Generating RTLIL representation for module `\LATCHNR'.
Generating RTLIL representation for module `\LATCHNS'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v
Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v' to AST representation.
Generating RTLIL representation for module `\GJC48'.
Successfully finished Verilog frontend.

-- Running command `hierarchy -top GJC48' --

3. Executing HIERARCHY pass (managing design hierarchy).

3.1. Analyzing design hierarchy..
Top module: \GJC48

3.2. Analyzing design hierarchy..
Top module: \GJC48
Removed 0 unused modules.

Dumping file hier_info.json ...
Process module "SOC_FPGA_INTF_DMA"
Dumping file port_info.json ...

End of script. Logfile hash: 5a1a282c91, CPU: user 0.05s system 0.02s, MEM: 112.07 MB peak
Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os)
Time spent: 95% 4x read_verilog (0 sec), 3% 1x analyze (0 sec), ...
125 changes: 125 additions & 0 deletions EDA-3164/GJC48/run_1/synth_1_1/analysis/hier_info.json
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{
"fileIDs": {
"1": "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v",
"2": "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v"
},
"hierTree": [
{
"file": "2",
"internalSignals": [
{
"name": "dma_ack_reg",
"range": {
"lsb": 0,
"msb": 3
},
"type": "LOGIC"
},
{
"name": "dma_req_reg",
"range": {
"lsb": 0,
"msb": 3
},
"type": "LOGIC"
}
],
"language": "SystemVerilog",
"line": 1,
"moduleInsts": [
{
"file": "2",
"instName": "dma_inst",
"line": 12,
"module": "SOC_FPGA_INTF_DMA",
"parameters": []
}
],
"ports": [
{
"direction": "Input",
"name": "clk",
"range": {
"lsb": 0,
"msb": 0
},
"type": "LOGIC"
},
{
"direction": "Input",
"name": "reset_n",
"range": {
"lsb": 0,
"msb": 0
},
"type": "LOGIC"
},
{
"direction": "Input",
"name": "dma_req_in",
"range": {
"lsb": 0,
"msb": 3
},
"type": "LOGIC"
},
{
"direction": "Output",
"name": "dma_ack_out",
"range": {
"lsb": 0,
"msb": 3
},
"type": "LOGIC"
}
],
"topModule": "GJC48"
}
],
"modules": {
"SOC_FPGA_INTF_DMA": {
"file": "1",
"language": "SystemVerilog",
"line": 861,
"module": "SOC_FPGA_INTF_DMA",
"ports": [
{
"direction": "Input",
"name": "DMA_REQ",
"range": {
"lsb": 0,
"msb": 3
},
"type": "LOGIC"
},
{
"direction": "Output",
"name": "DMA_ACK",
"range": {
"lsb": 0,
"msb": 3
},
"type": "LOGIC"
},
{
"direction": "Input",
"name": "DMA_CLK",
"range": {
"lsb": 0,
"msb": 0
},
"type": "LOGIC"
},
{
"direction": "Input",
"name": "DMA_RST_N",
"range": {
"lsb": 0,
"msb": 0
},
"type": "LOGIC"
}
]
}
}
}
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