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Updated RTL with register initialized with zero #259

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Sep 2, 2024
Merged

Updated RTL with register initialized with zero #259

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20 changes: 10 additions & 10 deletions EDA-3166/rtl/aes_192.v
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Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,8 @@ module aes_192 (clk, state, key, out);
input [127:0] state;
input [191:0] key;
output [127:0] out;
reg [127:0] s0;
reg [191:0] k0;
reg [127:0] s0=0;
reg [191:0] k0=0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
wire [191:0] k1, k2, k3, k4, k5, k6, k7, k8, k9, k10, k11;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b, k10b, k11b;
Expand Down Expand Up @@ -66,11 +66,11 @@ module expand_key_type_A_192 (clk, in, rcon, out_1, out_2);
input clk;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output reg [191:0] out_1=0;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
reg [31:0] k0a=0, k1a=0, k2a=0, k3a=0, k4a=0, k5a=0;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;

assign {k0, k1, k2, k3, k4, k5} = in;
Expand Down Expand Up @@ -102,11 +102,11 @@ endmodule
module expand_key_type_B_192 (clk, in, out_1, out_2);
input clk;
input [191:0] in;
output reg [191:0] out_1;
output reg [191:0] out_1=0;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v2, v3, v4, v5;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
reg [31:0] k0a=0, k1a=0, k2a=0, k3a=0, k4a=0, k5a=0;

assign {k0, k1, k2, k3, k4, k5} = in;

Expand All @@ -129,11 +129,11 @@ module expand_key_type_C_192 (clk, in, rcon, out_1, out_2);
input clk;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output reg [191:0] out_1=0;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v4, v5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
reg [31:0] k0a=0, k1a=0, k2a=0, k3a=0, k4a=0, k5a=0;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;

assign {k0, k1, k2, k3, k4, k5} = in;
Expand Down Expand Up @@ -164,11 +164,11 @@ module expand_key_type_D_192 (clk, in, rcon, out_1, out_2);
input clk;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output reg [191:0] out_1=0;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
reg [31:0] k0a=0, k1a=0, k2a=0, k3a=0, k4a=0, k5a=0;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;

assign {k0, k1, k2, k3, k4, k5} = in;
Expand Down
2 changes: 1 addition & 1 deletion EDA-3166/rtl/round.v
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Expand Up @@ -18,7 +18,7 @@
module one_round (clk, state_in, key, state_out);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
output reg [127:0] state_out=0;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
Expand Down
4 changes: 2 additions & 2 deletions EDA-3166/rtl/table.v
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Expand Up @@ -59,7 +59,7 @@ endmodule
module S (clk, in, out);
input clk;
input [7:0] in;
output reg [7:0] out;
output reg [7:0] out=0;

always @ (posedge clk)
case (in)
Expand Down Expand Up @@ -326,7 +326,7 @@ endmodule
module xS (clk, in, out);
input clk;
input [7:0] in;
output reg [7:0] out;
output reg [7:0] out=0;

always @ (posedge clk)
case (in)
Expand Down
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