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added 3 failing designs from yosys_daily #277

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merged 1 commit into from
Oct 2, 2024
Merged

added 3 failing designs from yosys_daily #277

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4 changes: 4 additions & 0 deletions EDA-3283/raptor_sdc.sdc
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create_clock -period 2.5 clk_i
set_input_delay 0 -clock clk_i [get_ports {*}]
set_output_delay 0 -clock clk_i [get_ports {*}]

66 changes: 66 additions & 0 deletions EDA-3283/raptor_tcl.tcl
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create_design hmac
target_device 1VG28
add_include_path ./rtl/
add_library_path ./rtl/
add_library_ext .v .sv
add_design_file -SV_2012 ./rtl/prim_secded_pkg.sv
add_design_file -SV_2012 ./rtl/prim_subreg_pkg.sv
add_design_file -SV_2012 ./rtl/prim_util_pkg.sv
add_design_file -SV_2012 ./rtl/pwrmgr_reg_pkg.sv
add_design_file -SV_2012 ./rtl/pwrmgr_pkg.sv
add_design_file -SV_2012 ./rtl/prim_ram_1p_pkg.sv
add_design_file -SV_2012 ./rtl/prim_mubi_pkg.sv
add_design_file -SV_2012 ./rtl/prim_pkg.sv
add_design_file -SV_2012 ./rtl/prim_cipher_pkg.sv
add_design_file -SV_2012 ./rtl/prim_alert_pkg.sv
add_design_file -SV_2012 ./rtl/prim_count_pkg.sv
add_design_file -SV_2012 ./rtl/jtag_pkg.sv
add_design_file -SV_2012 ./rtl/entropy_src_pkg.sv
add_design_file -SV_2012 ./rtl/edn_pkg.sv
add_design_file -SV_2012 ./rtl/top_pkg.sv
add_design_file -SV_2012 ./rtl/flash_ctrl_reg_pkg.sv
add_design_file -SV_2012 ./rtl/flash_ctrl_pkg.sv
add_design_file -SV_2012 ./rtl/flash_phy_pkg.sv
add_design_file -SV_2012 ./rtl/hmac_reg_pkg.sv
add_design_file -SV_2012 ./rtl/hmac_pkg.sv
add_design_file -SV_2012 ./rtl/lc_ctrl_pkg.sv
add_design_file -SV_2012 ./rtl/otp_ctrl_reg_pkg.sv
add_design_file -SV_2012 ./rtl/otp_ctrl_pkg.sv
add_design_file -SV_2012 ./rtl/tlul_pkg.sv
add_design_file -SV_2012 ./rtl/ast_pkg.sv
add_design_file -SV_2012 ./rtl/hmac.sv
add_design_file -SV_2012 ./rtl/hmac_core.sv
add_design_file -SV_2012 ./rtl/hmac_reg_top.sv
add_design_file -SV_2012 ./rtl/prim_alert_sender.sv
add_design_file -SV_2012 ./rtl/prim_buf.sv
add_design_file -SV_2012 ./rtl/prim_diff_decode.sv
add_design_file -SV_2012 ./rtl/prim_fifo_sync.sv
add_design_file -SV_2012 ./rtl/prim_flop_2sync.sv
add_design_file -SV_2012 ./rtl/prim_generic_buf.sv
add_design_file -SV_2012 ./rtl/prim_generic_flop.sv
add_design_file -SV_2012 ./rtl/prim_generic_flop_2sync.sv
add_design_file -SV_2012 ./rtl/prim_intr_hw.sv
add_design_file -SV_2012 ./rtl/prim_packer.sv
add_design_file -SV_2012 ./rtl/prim_secded_inv_39_32_dec.sv
add_design_file -SV_2012 ./rtl/prim_secded_inv_39_32_enc.sv
add_design_file -SV_2012 ./rtl/prim_secded_inv_64_57_dec.sv
add_design_file -SV_2012 ./rtl/prim_secded_inv_64_57_enc.sv
add_design_file -SV_2012 ./rtl/prim_subreg.sv
add_design_file -SV_2012 ./rtl/prim_subreg_ext.sv
add_design_file -SV_2012 ./rtl/sha2.sv
add_design_file -SV_2012 ./rtl/sha2_pad.sv
add_design_file -SV_2012 ./rtl/tlul_adapter_reg.sv
add_design_file -SV_2012 ./rtl/tlul_adapter_sram.sv
add_design_file -SV_2012 ./rtl/tlul_cmd_intg_chk.sv
add_design_file -SV_2012 ./rtl/tlul_data_integ_dec.sv
add_design_file -SV_2012 ./rtl/tlul_data_integ_enc.sv
add_design_file -SV_2012 ./rtl/tlul_err.sv
add_design_file -SV_2012 ./rtl/tlul_err_resp.sv
add_design_file -SV_2012 ./rtl/tlul_fifo_sync.sv
add_design_file -SV_2012 ./rtl/tlul_rsp_intg_gen.sv
add_design_file -SV_2012 ./rtl/tlul_socket_1n.sv
set_top_module hmac
add_constraint_file ./raptor_sdc.sdc
analyze
synth_options -effort high
synthesize delay
184 changes: 184 additions & 0 deletions EDA-3283/results_dir/hmac/hmac.ospr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- -->
<!--Copyright (c) 2021-2022 The Open-Source FPGA Foundation.-->
<Project Version="1.2.12">
<Configuration>
<Option Name="ID" Val="20241002014037589"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="Project Type" Val="0"/>
</Configuration>
<CompilerConfig>
<Opt Name="LibPath" Val=".././rtl/"/>
<Opt Name="IncludePath" Val=".././rtl/"/>
<Opt Name="LibExt" Val=".v .sv"/>
<Opt Name="Macro" Val=""/>
</CompilerConfig>
<SimulationConfig>
<Opt Name="LibPath" Val=""/>
<Opt Name="IncludePath" Val=""/>
<Opt Name="LibExt" Val=""/>
<Opt Name="Macro" Val=""/>
</SimulationConfig>
<IpConfig>
<Option Name="InstancePaths" Val=""/>
<Option Name="CatalogPaths" Val=""/>
<Option Name="InstanceCmds" Val=""/>
</IpConfig>
<FileSets>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="run_1/hmac.srcs/constrs_1">
<File Path="$OSRCDIR/../../raptor_sdc.sdc"/>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="run_1/hmac.srcs/sim_1">
<Config>
<Option Name="TopModule" Val=""/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="run_1/hmac.srcs/sources_1">
<File Path="$OSRCDIR/../../rtl/prim_secded_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_subreg_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_util_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/pwrmgr_reg_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/pwrmgr_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_ram_1p_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_mubi_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_cipher_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_alert_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_count_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/jtag_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/entropy_src_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/edn_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/top_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/flash_ctrl_reg_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/flash_ctrl_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/flash_phy_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/hmac_reg_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/hmac_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/lc_ctrl_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/otp_ctrl_reg_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/otp_ctrl_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/ast_pkg.sv"/>
<File Path="$OSRCDIR/../../rtl/hmac.sv"/>
<File Path="$OSRCDIR/../../rtl/hmac_core.sv"/>
<File Path="$OSRCDIR/../../rtl/hmac_reg_top.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_alert_sender.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_buf.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_diff_decode.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_fifo_sync.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_flop_2sync.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_generic_buf.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_generic_flop.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_generic_flop_2sync.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_intr_hw.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_packer.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_secded_inv_39_32_dec.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_secded_inv_39_32_enc.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_secded_inv_64_57_dec.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_secded_inv_64_57_enc.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_subreg.sv"/>
<File Path="$OSRCDIR/../../rtl/prim_subreg_ext.sv"/>
<File Path="$OSRCDIR/../../rtl/sha2.sv"/>
<File Path="$OSRCDIR/../../rtl/sha2_pad.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_adapter_reg.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_adapter_sram.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_cmd_intg_chk.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_data_integ_dec.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_data_integ_enc.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_err.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_err_resp.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_fifo_sync.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_rsp_intg_gen.sv"/>
<File Path="$OSRCDIR/../../rtl/tlul_socket_1n.sv"/>
<Group Id="11" Name="unit_0" Files="$OSRCDIR/../../rtl/prim_secded_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_1" Files="$OSRCDIR/../../rtl/prim_subreg_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_2" Files="$OSRCDIR/../../rtl/prim_util_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_3" Files="$OSRCDIR/../../rtl/pwrmgr_reg_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_4" Files="$OSRCDIR/../../rtl/pwrmgr_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_5" Files="$OSRCDIR/../../rtl/prim_ram_1p_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_6" Files="$OSRCDIR/../../rtl/prim_mubi_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_7" Files="$OSRCDIR/../../rtl/prim_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_8" Files="$OSRCDIR/../../rtl/prim_cipher_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_9" Files="$OSRCDIR/../../rtl/prim_alert_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_10" Files="$OSRCDIR/../../rtl/prim_count_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_11" Files="$OSRCDIR/../../rtl/jtag_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_12" Files="$OSRCDIR/../../rtl/entropy_src_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_13" Files="$OSRCDIR/../../rtl/edn_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_14" Files="$OSRCDIR/../../rtl/top_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_15" Files="$OSRCDIR/../../rtl/flash_ctrl_reg_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_16" Files="$OSRCDIR/../../rtl/flash_ctrl_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_17" Files="$OSRCDIR/../../rtl/flash_phy_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_18" Files="$OSRCDIR/../../rtl/hmac_reg_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_19" Files="$OSRCDIR/../../rtl/hmac_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_20" Files="$OSRCDIR/../../rtl/lc_ctrl_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_21" Files="$OSRCDIR/../../rtl/otp_ctrl_reg_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_22" Files="$OSRCDIR/../../rtl/otp_ctrl_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_23" Files="$OSRCDIR/../../rtl/tlul_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_24" Files="$OSRCDIR/../../rtl/ast_pkg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_25" Files="$OSRCDIR/../../rtl/hmac.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_26" Files="$OSRCDIR/../../rtl/hmac_core.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_27" Files="$OSRCDIR/../../rtl/hmac_reg_top.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_28" Files="$OSRCDIR/../../rtl/prim_alert_sender.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_29" Files="$OSRCDIR/../../rtl/prim_buf.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_30" Files="$OSRCDIR/../../rtl/prim_diff_decode.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_31" Files="$OSRCDIR/../../rtl/prim_fifo_sync.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_32" Files="$OSRCDIR/../../rtl/prim_flop_2sync.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_33" Files="$OSRCDIR/../../rtl/prim_generic_buf.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_34" Files="$OSRCDIR/../../rtl/prim_generic_flop.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_35" Files="$OSRCDIR/../../rtl/prim_generic_flop_2sync.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_36" Files="$OSRCDIR/../../rtl/prim_intr_hw.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_37" Files="$OSRCDIR/../../rtl/prim_packer.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_38" Files="$OSRCDIR/../../rtl/prim_secded_inv_39_32_dec.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_39" Files="$OSRCDIR/../../rtl/prim_secded_inv_39_32_enc.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_40" Files="$OSRCDIR/../../rtl/prim_secded_inv_64_57_dec.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_41" Files="$OSRCDIR/../../rtl/prim_secded_inv_64_57_enc.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_42" Files="$OSRCDIR/../../rtl/prim_subreg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_43" Files="$OSRCDIR/../../rtl/prim_subreg_ext.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_44" Files="$OSRCDIR/../../rtl/sha2.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_45" Files="$OSRCDIR/../../rtl/sha2_pad.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_46" Files="$OSRCDIR/../../rtl/tlul_adapter_reg.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_47" Files="$OSRCDIR/../../rtl/tlul_adapter_sram.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_48" Files="$OSRCDIR/../../rtl/tlul_cmd_intg_chk.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_49" Files="$OSRCDIR/../../rtl/tlul_data_integ_dec.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_50" Files="$OSRCDIR/../../rtl/tlul_data_integ_enc.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_51" Files="$OSRCDIR/../../rtl/tlul_err.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_52" Files="$OSRCDIR/../../rtl/tlul_err_resp.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_53" Files="$OSRCDIR/../../rtl/tlul_fifo_sync.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_54" Files="$OSRCDIR/../../rtl/tlul_rsp_intg_gen.sv" LibCommand="" LibName=""/>
<Group Id="11" Name="unit_55" Files="$OSRCDIR/../../rtl/tlul_socket_1n.sv" LibCommand="" LibName=""/>
<Config>
<Option Name="TopModule" Val="hmac"/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
</FileSets>
<Runs>
<Run Name="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="synth_1"/>
<Run Name="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="">
<Option Name="Compilation Flow" Val="Classic Flow"/>
<Option Name="Device" Val="1VG28"/>
<Option Name="Family" Val="Virgo"/>
<Option Name="LanguageVersion" Val="SYSTEMVERILOG_2005"/>
<Option Name="Package" Val="F484A"/>
<Option Name="Series" Val="Virgo"/>
<Option Name="TargetLanguage" Val="VERILOG"/>
</Run>
</Runs>
<Tasks Version="0.0.0">
<Task ID="0" Status="0" Enable="1"/>
<Task ID="1" Status="0" Enable="1"/>
<Task ID="6" Status="0" Enable="1"/>
<Task ID="10" Status="0" Enable="1"/>
<Task ID="15" Status="0" Enable="1"/>
<Task ID="19" Status="0" Enable="1"/>
<Task ID="20" Status="0" Enable="1"/>
<Task ID="21" Status="0" Enable="0"/>
<Task ID="23" Status="0" Enable="1"/>
<Task ID="28" Status="0" Enable="1"/>
<Task ID="31" Status="0" Enable="1"/>
<Task ID="34" Status="0" Enable="1"/>
<Task ID="37" Status="0" Enable="1"/>
</Tasks>
<Compiler Version="0.0.0" CompilerState="0"/>
</Project>
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