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Merge pull request #449 from os-fpga/task/EDA-3187/add_setup_lec_sim
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Task/eda 3187/add setup lec sim
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@NadeemYaseen
NadeemYaseen authored Nov 11, 2024
2 parents 4e172c0 + 1aa47da commit 03358bd
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Showing 5 changed files with 27 additions and 14 deletions.
5 changes: 5 additions & 0 deletions RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/raptor_run.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -206,6 +206,8 @@ parse_cga exit 1; }
[ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
[ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
[ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl
echo "setup_lec_sim">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
if [ "$post_synth_sim" == true ]; then
echo "# Open the input file in read mode">>raptor_tcl.tcl
echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl
Expand Down Expand Up @@ -259,6 +261,7 @@ parse_cga exit 1; }
else
echo ""
fi
[ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
echo "sta">>raptor_tcl.tcl
echo "power">>raptor_tcl.tcl
echo "bitstream $bitstream">>raptor_tcl.tcl
Expand All @@ -272,6 +275,8 @@ parse_cga exit 1; }
fi
fi

[ -f rtl/sim.v ] && sed -i -e "s|MEM_FILE_PATH|$PWD/rtl|g" rtl/sim.v

cd results_dir
echo "Device: $device">>results.log
echo "Strategy: $strategy">>results.log
Expand Down
14 changes: 7 additions & 7 deletions RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/rtl/sim.v
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Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,8 @@ module sim (
output wire serial_sink_ready,
input wire [7:0] serial_sink_data,
input wire sys_clk,
output reg [31:0] gpio_oe,
output reg [31:0] gpio_o,
output reg [31:0] gpio_oe=0,
output reg [31:0] gpio_o=0,
input wire [31:0] gpio_i
);

Expand Down Expand Up @@ -3175,7 +3175,7 @@ end
// Port 0 | Read: Sync | Write: ---- |
reg [31:0] mem[0:5391];
initial begin
$readmemh("mem.init", mem);
$readmemh("MEM_FILE_PATH/mem.init", mem);
end
reg [31:0] mem_dat0;
always @(posedge sys_clk_1) begin
Expand All @@ -3190,7 +3190,7 @@ assign main_simsoc_dat_r = mem_dat0;
// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
reg [31:0] mem_1[0:874];
initial begin
$readmemh("mem_1.init", mem_1);
$readmemh("MEM_FILE_PATH/mem_1.init", mem_1);
end
reg [9:0] mem_1_adr0;
always @(posedge sys_clk_1) begin
Expand All @@ -3213,7 +3213,7 @@ assign main_ram_dat_r = mem_1[mem_1_adr0];
// Port 0 | Read: Sync | Write: ---- |
reg [7:0] mem_2[0:36];
initial begin
$readmemh("mem_2.init", mem_2);
$readmemh("MEM_FILE_PATH/mem_2.init", mem_2);
end
reg [5:0] mem_2_adr0;
always @(posedge sys_clk_1) begin
Expand All @@ -3228,8 +3228,8 @@ assign builder_csr_bankarray_dat_r = mem_2[mem_2_adr0];
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage[0:15];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
reg [9:0] storage_dat0='d0;
reg [9:0] storage_dat1='d0;
always @(posedge sys_clk_1) begin
if (main_uart_tx_fifo_wrport_we)
storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w;
Expand Down
5 changes: 5 additions & 0 deletions RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_non_interactive_ip_litex/raptor_run.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -206,6 +206,8 @@ parse_cga exit 1; }
[ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
[ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
[ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl
echo "setup_lec_sim">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
if [ "$post_synth_sim" == true ]; then
echo "# Open the input file in read mode">>raptor_tcl.tcl
echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl
Expand Down Expand Up @@ -259,6 +261,7 @@ parse_cga exit 1; }
else
echo ""
fi
[ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
echo "sta">>raptor_tcl.tcl
echo "power">>raptor_tcl.tcl
echo "bitstream $bitstream">>raptor_tcl.tcl
Expand All @@ -272,6 +275,8 @@ parse_cga exit 1; }
fi
fi

[ -f rtl/sim.v ] && sed -i -e "s|MEM_FILE_PATH|$PWD/rtl|g" rtl/sim.v

cd results_dir
echo "Device: $device">>results.log
echo "Strategy: $strategy">>results.log
Expand Down
14 changes: 7 additions & 7 deletions RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_non_interactive_ip_litex/rtl/sim.v
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Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,8 @@ module sim (
output wire serial_sink_ready,
input wire [7:0] serial_sink_data,
input wire sys_clk,
output reg [31:0] gpio_oe,
output reg [31:0] gpio_o,
output reg [31:0] gpio_oe = 'd0,
output reg [31:0] gpio_o = 'd0,
input wire [31:0] gpio_i
);

Expand Down Expand Up @@ -3175,7 +3175,7 @@ end
// Port 0 | Read: Sync | Write: ---- |
reg [31:0] mem[0:5391];
initial begin
$readmemh("mem.init", mem);
$readmemh("MEM_FILE_PATH/mem.init", mem);
end
reg [31:0] mem_dat0;
always @(posedge sys_clk_1) begin
Expand All @@ -3190,7 +3190,7 @@ assign main_simsoc_dat_r = mem_dat0;
// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
reg [31:0] mem_1[0:874];
initial begin
$readmemh("mem_1.init", mem_1);
$readmemh("MEM_FILE_PATH/mem_1.init", mem_1);
end
reg [9:0] mem_1_adr0;
always @(posedge sys_clk_1) begin
Expand All @@ -3213,7 +3213,7 @@ assign main_ram_dat_r = mem_1[mem_1_adr0];
// Port 0 | Read: Sync | Write: ---- |
reg [7:0] mem_2[0:36];
initial begin
$readmemh("mem_2.init", mem_2);
$readmemh("MEM_FILE_PATH/mem_2.init", mem_2);
end
reg [5:0] mem_2_adr0;
always @(posedge sys_clk_1) begin
Expand All @@ -3228,8 +3228,8 @@ assign builder_csr_bankarray_dat_r = mem_2[mem_2_adr0];
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage[0:15];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
reg [9:0] storage_dat0 = 'd0;
reg [9:0] storage_dat1 = 'd0;
always @(posedge sys_clk_1) begin
if (main_uart_tx_fifo_wrport_we)
storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w;
Expand Down
3 changes: 3 additions & 0 deletions RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_verilog/raptor_run.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -259,6 +259,9 @@ parse_cga exit 1; }
else
echo ""
fi
echo "setup_lec_sim">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
echo "sta">>raptor_tcl.tcl
echo "power">>raptor_tcl.tcl
echo "bitstream $bitstream">>raptor_tcl.tcl
Expand Down

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