Skip to content

Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.

License

Notifications You must be signed in to change notification settings

os-fpga/litex_reference_designs

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Litex Reference Designs

Litex Reference designs is a python package providing example design for Raptor toolchain based upon litex.

├── docs
├── example_designs
│   ├── vexriscv_axi_gpio
│   ├── vexriscv_axi_ram
│   └── vexriscv_hello_world
|    
├── rtl_designs
    ├── vexriscv_axi_ram
    ├── vexriscv_plic_clint
``` └── vexriscv_axi_cdma 


## Raptor_example_designs

This contains example designs with application code to run with LiteX. Every test has a separate README for assistance.


About

Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.

Topics

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published