Digital Logic Circuit Simulator

This project simulates the behavior of digital circuits using Verilog-like descriptions and generates a waveform visualization of the simulation results. The simulator processes a .v file describing the circuit, a .stim file containing input changes over time, and outputs the resulting simulation data to output.sim.

Project Structure

• main.cpp: The main entry point for the simulator. It reads the Verilog file, processes the stimulus file, and simulates the digital circuit.
• LogicGate.cpp: Implements the behavior of logic gates (e.g., AND, OR, XOR) and their interactions with inputs, outputs, and wires.
• LogicGate.hpp: Header file defining the logicGate class and ioVar structure.
• Circuit.v: Verilog-like file describing the circuit. Defines inputs, outputs, wires, and gates.
• Circuit.stim: Stimulus file specifying input changes over time for testing the circuit.
• output.sim: Generated file containing the time-stamped output values of the circuit simulation.
• waveform.py: Python script to visualize the simulation results as a waveform using Matplotlib.

Prerequisites

• C++ compiler (e.g., g++).
• Python 3.x with pandas and matplotlib installed.

Example Files

Circuit.v

Example of a Verilog-like file defining a circuit:

module circuit_3(a, b, cin, sum, carry, xor_out);
    input a;
    input b;
    input cin;
    output sum;
    output carry;
    output xor_out;

    wire w1;
    wire w2;
    wire w3;

    xor #(5) g0 (w1, a, b);
    and #(3) g1 (w2, a, b);
    xor #(5) g2 (sum, w1, cin);
    and #(3) g3 (w3, w1, cin);
    or #(4) g4 (carry, w2, w3);
    xor #(5) g5 (xor_out, a, b, cin);
endmodule

Circuit.stim

Example of a stimulus file specifying input changes over time:

#0 a=0; b=0; cin=0;
#100 a=0; b=0; cin=1;
#100 a=0; b=1; cin=0;
#100 a=0; b=1; cin=1;
#100 a=1; b=0; cin=0;
#100 a=1; b=0; cin=1;
#100 a=1; b=1; cin=0;
#100 a=1; b=1; cin=1;

output.sim

Sample output file generated by the simulator:

0,sum,0
0,carry,0
0,xor_out,0
100,sum,1
100,xor_out,1
300,sum,0
300,carry,1
300,xor_out,0
400,sum,1
400,carry,0
400,xor_out,1
500,sum,0
500,carry,1
500,xor_out,0
700,sum,1
700,xor_out,1