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Updated VPWR/VGND ports inside GL_TEST to match new template tb.v test #70: Commit 20368bb pushed by rejunity
November 8, 2024 21:35 47s main
main
November 8, 2024 21:35 47s
Updated VPWR/VGND ports inside GL_TEST to match new template tb.v test #69: Commit 20368bb pushed by rejunity
November 8, 2024 21:18 40s tt09
tt09
November 8, 2024 21:18 40s
Docs: MUX pins test #68: Commit 53d893b pushed by rejunity
November 8, 2024 20:52 42s main
main
November 8, 2024 20:52 42s
Docs: MUX pins test #67: Commit 53d893b pushed by rejunity
November 3, 2024 10:05 59s tt09
tt09
November 3, 2024 10:05 59s
iHP0p2 new config.json with 0.75 density (upped from 70 just in case)… test #66: Commit b33b073 pushed by rejunity
November 2, 2024 23:40 1m 7s ttihp0p2
ttihp0p2
November 2, 2024 23:40 1m 7s
The whole TT07 chip in OASIS format test #65: Commit a8b2127 pushed by rejunity
November 2, 2024 23:24 35s tt07-tapeout
tt07-tapeout
November 2, 2024 23:24 35s
Update README.md test #64: Commit 0d51915 pushed by rejunity
August 2, 2024 11:09 38s main
main
August 2, 2024 11:09 38s
Added recent DYI Z80 computer kits to list of good test-cases test #63: Commit 5297295 pushed by rejunity
July 31, 2024 13:40 35s main
main
July 31, 2024 13:40 35s
CI2406 tapeout GDS test #62: Commit 4f2ab29 pushed by rejunity
June 10, 2024 07:06 55s ci2406
ci2406
June 10, 2024 07:06 55s
Fixed stupid dangerous mistake in io_out initialisation! (introduced … test #61: Commit 51fefd5 pushed by rejunity
June 6, 2024 14:42 52s ci2406
ci2406
June 6, 2024 14:42 52s
Separated early signal control lines test #60: Commit c5312d6 pushed by rejunity
June 6, 2024 14:34 39s ci2406
ci2406
June 6, 2024 14:34 39s
WR is always normal. Custom settings to prolong MREQ & IORQ. test #59: Commit d22bcf7 pushed by rejunity
June 6, 2024 14:25 1m 1s ci2406
ci2406
June 6, 2024 14:25 1m 1s
Optional half cycle earlier MREQ, IORQ, RD, WR signals test #58: Commit f802101 pushed by rejunity
June 5, 2024 14:49 35s ci2406
ci2406
June 5, 2024 14:49 35s
Enalbed TV80_REFRESH test #57: Commit 3c2be84 pushed by rejunity
June 5, 2024 12:19 35s ci2406
ci2406
June 5, 2024 12:19 35s
Enalbed TV80_REFRESH test #56: Commit d3a7953 pushed by rejunity
June 5, 2024 12:01 34s main
main
June 5, 2024 12:01 34s
Fix stupid test #55: Commit 9436cbd pushed by rejunity
June 5, 2024 10:55 38s ci2406
ci2406
June 5, 2024 10:55 38s
5th iteration of Z80 to Caravel mapping. test #54: Commit a31522c pushed by rejunity
June 5, 2024 10:49 34s ci2406
ci2406
June 5, 2024 10:49 34s
Prep for CI2406 test #53: Commit e034540 pushed by rejunity
June 4, 2024 07:46 31s main
main
June 4, 2024 07:46 31s
Made output mux asynchronous (non-clocked) and driven by excternal input test #52: Commit 7f155e9 pushed by rejunity
June 1, 2024 18:38 41s main
main
June 1, 2024 18:38 41s
3rd iteration of Z80 to Caravel mapping to minimise wires crossing on… test #51: Commit bcd2685 pushed by rejunity
May 30, 2024 06:34 38s ci2406
ci2406
May 30, 2024 06:34 38s
Whitespace test #50: Commit e01e28a pushed by rejunity
May 27, 2024 23:22 1m 8s ci2406
ci2406
May 27, 2024 23:22 1m 8s
Pin revision, potentially less cross-over on the bottom part of the chip test #49: Commit c97c09b pushed by rejunity
May 27, 2024 23:18 31s ci2406
ci2406
May 27, 2024 23:18 31s
Databus mapping in the weird z80 way (to reduce wires crossing) test #48: Commit 288558f pushed by rejunity
May 27, 2024 19:58 33s ci2406
ci2406
May 27, 2024 19:58 33s
ChipIgnite QFN46 pin layout test #47: Commit 3956114 pushed by rejunity
May 27, 2024 19:21 32s ci2406
ci2406
May 27, 2024 19:21 32s
Test for chipignite test #46: Commit 79b4450 pushed by rejunity
May 27, 2024 14:51 37s ci2406
ci2406
May 27, 2024 14:51 37s