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5th iteration of Z80 to Caravel mapping. test #54: Commit a31522c pushed by rejunity
June 5, 2024 10:49 34s ci2406
ci2406
June 5, 2024 10:49 34s
Prep for CI2406 docs #53: Commit e034540 pushed by rejunity
June 4, 2024 07:46 1m 19s main
main
June 4, 2024 07:46 1m 19s
Prep for CI2406 gds #53: Commit e034540 pushed by rejunity
June 4, 2024 07:46 16m 5s main
main
June 4, 2024 07:46 16m 5s
Prep for CI2406 test #53: Commit e034540 pushed by rejunity
June 4, 2024 07:46 31s main
main
June 4, 2024 07:46 31s
Made output mux asynchronous (non-clocked) and driven by excternal input docs #52: Commit 7f155e9 pushed by rejunity
June 1, 2024 18:38 1m 9s main
main
June 1, 2024 18:38 1m 9s
Made output mux asynchronous (non-clocked) and driven by excternal input test #52: Commit 7f155e9 pushed by rejunity
June 1, 2024 18:38 41s main
main
June 1, 2024 18:38 41s
Made output mux asynchronous (non-clocked) and driven by excternal input gds #52: Commit 7f155e9 pushed by rejunity
June 1, 2024 18:38 15m 49s main
main
June 1, 2024 18:38 15m 49s
3rd iteration of Z80 to Caravel mapping to minimise wires crossing on… test #51: Commit bcd2685 pushed by rejunity
May 30, 2024 06:34 38s ci2406
ci2406
May 30, 2024 06:34 38s
3rd iteration of Z80 to Caravel mapping to minimise wires crossing on… gds #51: Commit bcd2685 pushed by rejunity
May 30, 2024 06:34 16m 22s ci2406
ci2406
May 30, 2024 06:34 16m 22s
3rd iteration of Z80 to Caravel mapping to minimise wires crossing on… docs #51: Commit bcd2685 pushed by rejunity
May 30, 2024 06:34 1m 32s ci2406
ci2406
May 30, 2024 06:34 1m 32s
Whitespace gds #50: Commit e01e28a pushed by rejunity
May 27, 2024 23:22 16m 4s ci2406
ci2406
May 27, 2024 23:22 16m 4s
Whitespace test #50: Commit e01e28a pushed by rejunity
May 27, 2024 23:22 1m 8s ci2406
ci2406
May 27, 2024 23:22 1m 8s
Whitespace docs #50: Commit e01e28a pushed by rejunity
May 27, 2024 23:22 1m 10s ci2406
ci2406
May 27, 2024 23:22 1m 10s
Pin revision, potentially less cross-over on the bottom part of the chip gds #49: Commit c97c09b pushed by rejunity
May 27, 2024 23:18 16m 0s ci2406
ci2406
May 27, 2024 23:18 16m 0s
Pin revision, potentially less cross-over on the bottom part of the chip docs #49: Commit c97c09b pushed by rejunity
May 27, 2024 23:18 1m 22s ci2406
ci2406
May 27, 2024 23:18 1m 22s
Pin revision, potentially less cross-over on the bottom part of the chip test #49: Commit c97c09b pushed by rejunity
May 27, 2024 23:18 31s ci2406
ci2406
May 27, 2024 23:18 31s
Databus mapping in the weird z80 way (to reduce wires crossing) docs #48: Commit 288558f pushed by rejunity
May 27, 2024 19:58 1m 9s ci2406
ci2406
May 27, 2024 19:58 1m 9s
Databus mapping in the weird z80 way (to reduce wires crossing) gds #48: Commit 288558f pushed by rejunity
May 27, 2024 19:58 15m 42s ci2406
ci2406
May 27, 2024 19:58 15m 42s
Databus mapping in the weird z80 way (to reduce wires crossing) test #48: Commit 288558f pushed by rejunity
May 27, 2024 19:58 33s ci2406
ci2406
May 27, 2024 19:58 33s
ChipIgnite QFN46 pin layout gds #47: Commit 3956114 pushed by rejunity
May 27, 2024 19:21 15m 37s ci2406
ci2406
May 27, 2024 19:21 15m 37s
ChipIgnite QFN46 pin layout test #47: Commit 3956114 pushed by rejunity
May 27, 2024 19:21 32s ci2406
ci2406
May 27, 2024 19:21 32s
ChipIgnite QFN46 pin layout docs #47: Commit 3956114 pushed by rejunity
May 27, 2024 19:21 1m 11s ci2406
ci2406
May 27, 2024 19:21 1m 11s
Test for chipignite gds #46: Commit 79b4450 pushed by rejunity
May 27, 2024 14:51 16m 10s ci2406
ci2406
May 27, 2024 14:51 16m 10s
Test for chipignite docs #46: Commit 79b4450 pushed by rejunity
May 27, 2024 14:51 1m 25s ci2406
ci2406
May 27, 2024 14:51 1m 25s
Test for chipignite test #46: Commit 79b4450 pushed by rejunity
May 27, 2024 14:51 37s ci2406
ci2406
May 27, 2024 14:51 37s