Update Zbk* extensions

arch/inst/Zbkb/brev8.yaml

@@ -3,9 +3,9 @@
 $schema: inst_schema.json#
 kind: instruction
 name: brev8
-long_name: No synopsis available.
+long_name: Reverse the bits in each byte of a source register.
 description: |
-  No description available.
+  This instruction reverses the order of the bits in every byte of a register. 
 definedBy:
   anyOf: [B, Zbkb, Zk, Zkn, Zks]
 assembly: xd, xs1
@@ -23,3 +23,24 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg input = X[rs1];
+  XReg output = 0;
+
+  for(U32 i=0; i<(xlen()-8); i = i+8) {
+    for(U32 j=0; j<8; j = j+1) {
+      output[(i*8)+(7-j)] = input[(i*8)+j];
+    }
+  }
+
+  X[rd] = output;
+
+sail(): |
+  result : xlenbits = EXTZ(0b0);
+  foreach (i from 0 to sizeof(xlen) by 8) {
+    result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]);
+  };
+  X(rd) = result;

arch/inst/Zbkb/unzip.yaml

@@ -3,9 +3,11 @@
 $schema: inst_schema.json#
 kind: instruction
 name: unzip
-long_name: No synopsis available.
+long_name: Inverse of Zip.
 description: |
-  No description available.
+  This instruction gathers bits from the high and low halves of the source word into odd/even bit
+  positions in the destination word. It is the inverse of the zip instruction. This instruction is
+  available only on RV32.
 definedBy:
   anyOf: [B, Zbkb, Zk, Zkn, Zks]
 assembly: xd, xs1
@@ -24,3 +26,24 @@ access:
 data_independent_timing: false
 base: 32
 operation(): |
+  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg input = X[rs1];
+  XReg output = 0;
+
+  for(U32 i=0; i<(xlen()/2-1); i = i+1) {
+    output[i] = input[2*i];
+    output[i+xlen()/2] = input[2*i+1];
+  }
+
+  X[rd] = output;
+
+
+sail(): |
+
+  foreach (i from 0 to xlen/2-1) {
+    X(rd)[i] = X(rs1)[2*i];
+    X(rd)[i+xlen/2] = X(rs1)[2*i+1];
+  }

arch/inst/Zbkb/zip.yaml

@@ -3,9 +3,11 @@
 $schema: inst_schema.json#
 kind: instruction
 name: zip
-long_name: No synopsis available.
+long_name: Gather odd and even bits of the source word into upper/lower halves of the destination.
 description: |
-  No description available.
+  This instruction scatters all of the odd and even bits of a source word into the high and low halves
+  of a destination word. It is the inverse of the unzip instruction. This instruction is available only on
+  RV32.
 definedBy:
   anyOf: [B, Zbkb, Zk, Zkn, Zks]
 assembly: xd, xs1
@@ -24,3 +26,23 @@ access:
 data_independent_timing: false
 base: 32
 operation(): |
+  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg input = X[rs1];
+  XReg output = 0;
+
+  for(U32 i=0; i<(xlen()/2-1); i = i+1){
+    output[2*i] = input[i];
+    output[2*i+1] = input[i+xlen()/2];
+  }
+
+  X[rd] = output;
+
+sail(): |
+
+  foreach (i from 0 to xlen/2-1) {
+    X(rd)[2*i] = X(rs1)[i];
+    X(rd)[2*i+1] = X(rs1)[i+xlen/2];
+  }

arch/inst/Zbkx/xperm4.yaml

@@ -3,9 +3,11 @@
 $schema: inst_schema.json#
 kind: instruction
 name: xperm4
-long_name: No synopsis available.
+long_name: Nibble-wise lookup of indicies into a vector.
 description: |
-  No description available.
+  The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 4-bit
+  elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in
+  rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.
 definedBy:
   anyOf: [B, Zbkx, Zk, Zkn, Zks]
 assembly: xd, xs1, xs2
@@ -25,3 +27,33 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg input1 = X[rs1];
+  XReg input2 = X[rs2];
+  XReg output = 0;
+
+  for(U32 i=0; i<(xlen()-4); i = i+4) {
+    XReg index = input2[i+3:i];
+    if(4*index < xlen()) {
+      output[i+3:i] = input1[4*index+3:4*index];
+    }
+  }
+
+  X[rd] = output;
+
+sail(): |
+  val xperm4_lookup : (bits(4), xlenbits) -> bits(4)
+  function xperm4_lookup (idx, lut) = {
+    (lut >> (idx @ 0b00))[3..0]
+  }
+  function clause execute ( XPERM_4 (rs2,rs1,rd)) = {
+    result : xlenbits = EXTZ(0b0);
+    foreach(i from 0 to xlen by 4) {
+      result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1));
+    };
+    X(rd) = result;
+    RETIRE_SUCCESS
+  }

arch/inst/Zbkx/xperm8.yaml

@@ -3,9 +3,11 @@
 $schema: inst_schema.json#
 kind: instruction
 name: xperm8
-long_name: No synopsis available.
+long_name: Byte-wise lookup of indicies into a vector.
 description: |
-  No description available.
+  The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 8-bit
+  elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in
+  rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.
 definedBy:
   anyOf: [B, Zbkx, Zk, Zkn, Zks]
 assembly: xd, xs1, xs2
@@ -25,3 +27,34 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg input1 = X[rs1];
+  XReg input2 = X[rs2];
+  XReg output = 0;
+
+  for(U32 i=0; i<(xlen()-8); i = i+8) {
+    XReg index = input2[i+7:i];
+    if(8*index < xlen()) {
+      output[i+7:i] = input1[8*index+7:8*index];
+    }
+  }
+
+  X[rd] = output;
+
+sail(): |
+
+  val xperm8_lookup : (bits(8), xlenbits) -> bits(8)
+  function xperm8_lookup (idx, lut) = {
+    (lut >> (idx @ 0b00))[7..0]
+  }
+  function clause execute ( XPERM_8 (rs2,rs1,rd)) = {
+    result : xlenbits = EXTZ(0b0);
+    foreach(i from 0 to xlen by 8) {
+      result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1));
+    };
+    X(rd) = result;
+    RETIRE_SUCCESS
+  }