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Removed section on non-idempotent memory handling (#38)
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christian-herber-nxp authored Jul 4, 2024
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Expand Up @@ -110,14 +110,6 @@ From a software perspective the load/store pair instructions appears as:
*** The bytes may be grouped into larger accesses.
*** Any of the bytes may be stored multiple times.

=== Non-idempotent memory handling

An implementation may have a requirement to issue a load/store pair instruction to non-idempotent memory.

If an implementation of a hart does not support Zilsd instructions to non-idempotent memories, the hart may use an idempotency PMA to detect it and take a load or store access fault exception in order to avoid unpredictable results.

Software should only use these instructions on non-idempotent memory regions when software can tolerate the required memory accesses being issued repeatedly in the case that they cause exceptions.

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=== Instructions
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