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avsdpll_1v8
avsdpll_1v8 PublicForked from lakshmi-sathi/avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room tempe…
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ROUTER-1-3
ROUTER-1-3 PublicForked from kumarswamy12/ROUTER-1-3
verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL
SystemVerilog
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ARM_AMBA_Design
ARM_AMBA_Design PublicForked from lucky-wfw/ARM_AMBA_Design
Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
Verilog
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