Merge pull request #27 from YdrMaster/main

Improve backward comptability to older QEMU; fix issue on not producing time interrupt on machine mode
rustsbi · Jul 21, 2022 · 05cbb4d · 05cbb4d
2 parents e5ab409 + 62bee35
commit 05cbb4d
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Showing 12 changed files with 168 additions and 147 deletions.
diff --git a/.vscode/settings.json b/.vscode/settings.json
@@ -6,7 +6,7 @@
     "rust.all_targets": false,
     // For Rust Analyzer plugin users:
     "rust-analyzer.cargo.target": "riscv64imac-unknown-none-elf",
-    "rust-analyzer.checkOnSave.enable": false,
+    "rust-analyzer.checkOnSave.allTargets": false,
     // Other settings
     // For clap
     "rust-analyzer.procMacro.attributes.enable": true,

diff --git a/Cargo.lock b/Cargo.lock
diff --git a/rustsbi-qemu/Cargo.toml b/rustsbi-qemu/Cargo.toml
@@ -6,10 +6,12 @@ edition = "2021"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
-rustsbi = { git = "https://github.com/YdrMaster/rustsbi.git", rev = "bd3c092" }
+rustsbi = { git = "https://github.com/rustsbi/rustsbi", rev = "af60b02", features = [
+    "legacy",
+] }
 riscv = "0.8"
 spin = "0.9"
 r0 = "1"
 uart_16550 = "0.2"
-dtb-walker = "0.1.1"
+dtb-walker = "=0.2.0-alpha.3"
 qemu-exit = "3.0"
diff --git a/rustsbi-qemu/src/clint.rs b/rustsbi-qemu/src/clint.rs
@@ -55,6 +55,8 @@ impl Timer for Clint {
     #[inline]
     fn set_timer(&self, time_value: u64) {
         unsafe {
+            riscv::register::mip::clear_stimer();
+            riscv::register::mie::set_mtimer();
             ((self.base as *mut u8).offset(0x4000) as *mut u64)
                 .add(hart_id())
                 .write_volatile(time_value);

diff --git a/rustsbi-qemu/src/device_tree.rs b/rustsbi-qemu/src/device_tree.rs
@@ -27,13 +27,13 @@ impl<const N: usize> Display for StringInline<N> {
 
 /// 解析设备树。
 pub(crate) fn parse(opaque: usize) -> BoardInfo {
-    use dtb_walker::{Dtb, DtbObj, Property, WalkOperation::*};
-    const CPUS: &[u8] = b"cpus";
-    const MEMORY: &[u8] = b"memory";
-    const SOC: &[u8] = b"soc";
-    const UART: &[u8] = b"uart";
-    const TEST: &[u8] = b"test";
-    const CLINT: &[u8] = b"clint";
+    use dtb_walker::{Dtb, DtbObj, HeaderError as E, Property, Str, WalkOperation::*};
+    const CPUS: &str = "cpus";
+    const MEMORY: &str = "memory";
+    const SOC: &str = "soc";
+    const UART: &str = "uart";
+    const TEST: &str = "test";
+    const CLINT: &str = "clint";
 
     let mut ans = BoardInfo {
         dtb: opaque..opaque,
@@ -44,37 +44,42 @@ pub(crate) fn parse(opaque: usize) -> BoardInfo {
         test: 0..0,
         clint: 0..0,
     };
-    let dtb = unsafe { Dtb::from_raw_parts(opaque as _) }.unwrap();
+    let dtb = unsafe {
+        Dtb::from_raw_parts_filtered(opaque as _, |e| {
+            matches!(e, E::Misaligned(4) | E::LastCompVersion(16))
+        })
+    }
+    .unwrap();
     ans.dtb.end += dtb.total_size();
-    dtb.walk(|path, obj| match obj {
+    dtb.walk(|ctx, obj| match obj {
         DtbObj::SubNode { name } => {
-            let current = path.last();
-            if current.is_empty() {
-                if name == CPUS || name == SOC || name.starts_with(MEMORY) {
+            let current = ctx.name();
+            if ctx.is_root() {
+                if name == Str::from(CPUS) || name == Str::from(SOC) || name.starts_with(MEMORY) {
                     StepInto
                 } else {
                     StepOver
                 }
-            } else if current == SOC {
+            } else if current == Str::from(SOC) {
                 if name.starts_with(UART) || name.starts_with(TEST) || name.starts_with(CLINT) {
                     StepInto
                 } else {
                     StepOver
                 }
             } else {
-                if current == CPUS && name.starts_with(b"cpu@") {
+                if current == Str::from(CPUS) && name.starts_with("cpu@") {
                     ans.smp += 1;
                 }
                 StepOver
             }
         }
-        DtbObj::Property(Property::Model(model)) if path.last().is_empty() => {
+        DtbObj::Property(Property::Model(model)) if ctx.is_root() => {
             ans.model.0 = model.as_bytes().len();
             ans.model.1[..ans.model.0].copy_from_slice(model.as_bytes());
             StepOver
         }
         DtbObj::Property(Property::Reg(mut reg)) => {
-            let node = path.last();
+            let node = ctx.name();
             if node.starts_with(UART) {
                 ans.uart = reg.next().unwrap();
                 StepOut