code clean up

system_vitis_unified_hls.mk

@@ -20,13 +20,12 @@ endif
 
 # Project Build Directory
 ifndef OUT_DIR
-export OUT_DIR  = $(abspath $(TOP_DIR)/build/$(PROJECT))
+export OUT_DIR  = $(abspath $(TOP_DIR)/build/$(PROJECT))_workspace
 endif
 
-# Synthesis Variables
+# Build System Variables
 export VIVADO_VERSION   = $(shell vivado -version | grep -Po "v(\d+\.)+\d+" | cut -c2-)
 export RUCKUS_DIR       = $(TOP_DIR)/submodules/ruckus
-export SOURCE_DEPEND    = $(OUT_DIR)/$(PROJECT)_sources.txt
 
 # Source Files
 ifndef SRC_FILE
@@ -46,7 +45,7 @@ export PRJ_VERSION = v$(EXPORT_VERSION)
 
 # Specifies if we need to modify the ip/component.xml to support "all" FPGA family types
 ifndef ALL_XIL_FAMILY
-export ALL_XIL_FAMILY = 0
+export ALL_XIL_FAMILY = 1
 endif
 
 include $(TOP_DIR)/submodules/ruckus/system_shared.mk

vitis/hls/build.py

@@ -11,10 +11,14 @@
 
 import vitis
 import os
+import shutil
+import zipfile
 
 # Project variables
 workspace = os.getenv("OUT_DIR")
 comp_name = os.getenv("PROJECT")
+proj_zip  = f'{workspace}/{comp_name}/{comp_name}/{comp_name}.zip'
+build_zip = f'{os.getenv("PROJ_DIR")}/ip/{comp_name}.zip'
 
 # Create a client object
 client = vitis.create_client()
@@ -39,3 +43,48 @@
 
 # Close the client connection and terminate the vitis server
 vitis.dispose()
+
+# Check if ALL_XIL_FAMILY is enabled
+if int(os.getenv("ALL_XIL_FAMILY")) > 0:
+
+    # Over the .ZIP file and decompress it
+    ip_path = f'{workspace}/ip'
+    os.system( f'rm -rf {ip_path}' )
+    os.system( f'mkdir {ip_path}' )
+    os.system( f'unzip {proj_zip} -d {ip_path}' )
+
+    # Read and modify component.xml
+    component_path = f'{ip_path}/component.xml'
+    temp_path = f'{ip_path}/component.temp'
+    with open(component_path, 'r') as infile, open(temp_path, 'w') as outfile:
+        xil_family = """
+<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">zynquplusRFSOC</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
+"""
+        for line in infile:
+            if 'xilinx:family' in line:
+                outfile.write(xil_family)
+            else:
+                outfile.write(line)
+
+    # Replace the original component.xml with the modified one
+    shutil.move(temp_path, component_path)
+
+    # Compress the modify IP directory to the target's image directory
+    os.system( f'bash -c "cd {ip_path}; zip -r {build_zip} *"' )
+
+else:
+    # Copy the .ZIP file to the local ip/ directory
+    shutil.copy(proj_zip, build_zip)
+
+print( f'\n\n\nHLS output file: {build_zip}' )