Skip to content

Commit

Permalink
Merge pull request #296 from slaclab/pre-release
Browse files Browse the repository at this point in the history
Release Candidate v4.8.0
  • Loading branch information
ruck314 authored Apr 11, 2023
2 parents e0652cf + 452ac38 commit d657b0a
Show file tree
Hide file tree
Showing 7 changed files with 199 additions and 6 deletions.
4 changes: 2 additions & 2 deletions fabulous/build.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@
##############################################################################

# Load RUCKUS environment and library
source $::env(RUCKUS_DC_DIR)/proc.tcl
source $::env(RUCKUS_DC_DIR)/env_var.tcl
source $::env(RUCKUS_FAB_DIR)/proc.tcl
source $::env(RUCKUS_FAB_DIR)/env_var.tcl

# Run the user configuration script
SourceTclFile ${PROJ_DIR}/fabulous.tcl
Expand Down
24 changes: 24 additions & 0 deletions ghdl/import.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
#!/usr/bin/tclsh
##############################################################################
## This file is part of 'SLAC Firmware Standard Library'.
## It is subject to the license terms in the LICENSE.txt file found in the
## top-level directory of this distribution and at:
## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
## No part of 'SLAC Firmware Standard Library', including this file,
## may be copied, modified, propagated, or distributed except according to
## the terms contained in the LICENSE.txt file.
##############################################################################

# Load RUCKUS environment and library
source $::env(RUCKUS_PROC_TCL_COMBO)

# Init the global variable
set ::DIR_PATH ""

# Remove the existing source directories
exec rm -rf $::env(OUT_DIR)/SRC_VHDL
exec rm -rf $::env(OUT_DIR)/SRC_VERILOG
exec rm -rf $::env(OUT_DIR)/SRC_SVERILOG

# Load the top-level ruckus.tcl
loadRuckusTcl $::env(PROJ_DIR)
165 changes: 165 additions & 0 deletions ghdl/proc.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,165 @@
##############################################################################
## This file is part of 'SLAC Firmware Standard Library'.
## It is subject to the license terms in the LICENSE.txt file found in the
## top-level directory of this distribution and at:
## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
## No part of 'SLAC Firmware Standard Library', including this file,
## may be copied, modified, propagated, or distributed except according to
## the terms contained in the LICENSE.txt file.
##############################################################################

source $::env(RUCKUS_DIR)/shared/proc.tcl

## Returns the FPGA family string
proc getFpgaFamily { } {
# Legacy Vivado function: not-supported
return "not-supported"
}

## Returns the FPGA family string
proc getFpgaArch { } {
# Legacy Vivado function: not-supported
return "not-supported"
}

## Returns true is Versal
proc isVersal { } {
# Legacy Vivado function: not-supported
return false;
}

###############################################################
#### Loading Source Code Functions ############################
###############################################################

## Open ruckus.tcl file
proc loadRuckusTcl { filePath {flags ""} } {
puts "loadRuckusTcl: ${filePath} ${flags}"
# Make a local copy of global variable
set LOC_PATH $::DIR_PATH
# Make a local copy of global variable
set ::DIR_PATH ${filePath}
# Open the TCL file
if { [file exists ${filePath}/ruckus.tcl] == 1 } {
source ${filePath}/ruckus.tcl
} else {
puts "\n\n\n\n\n********************************************************"
puts "loadRuckusTcl: ${filePath}/ruckus.tcl doesn't exist"
puts "********************************************************\n\n\n\n\n"
exit -1
}
# Revert the global variable back to original value
set ::DIR_PATH ${LOC_PATH}
}

## Update source file lists
proc UpdateSrcFileLists {filepath lib} {
set path ${filepath}
set fileExt [file extension ${path}]
set fbasename [file tail ${path}]
if { ${fileExt} eq {.vhd} ||
${fileExt} eq {.vhdl} } {
set SRC_TYPE "SRC_VHDL"
} elseif {
${fileExt} eq {.v} ||
${fileExt} eq {.vh} } {
set SRC_TYPE "SRC_VERILOG"
} else {
set SRC_TYPE "SRC_SVERILOG"
}
exec mkdir -p $::env(OUT_DIR)/${SRC_TYPE}
exec mkdir -p $::env(OUT_DIR)/${SRC_TYPE}/${lib}
exec ln -s ${path} $::env(OUT_DIR)/${SRC_TYPE}/${lib}/${fbasename}
}

## Function to load RTL files
proc loadSource args {

# Strip out the -sim_only flag
if {[string match {*-sim_only*} $args]} {
set args [string map {"-sim_only" ""} $args]
# Not support simulation source code in design compiler yet
return
}

# Parse the list of args
array set params $args

if {![info exists params(-path)]} {
set has_path 0
} else {
set has_path 1
}

if {![info exists params(-dir)]} {
set has_dir 0
} else {
set has_dir 1
}

if {![info exists params(-lib)]} {
set lib "work"
} else {
set lib $params(-lib)
}

# Check for error state
if {${has_path} && ${has_dir}} {
puts "\n\n\n\n\n********************************************************"
puts "loadSource: Cannot specify both -path and -dir"
puts "********************************************************\n\n\n\n\n"
exit -1
# Load a single file
} elseif {$has_path} {
# Check if file doesn't exist
if { [file exists $params(-path)] != 1 } {
puts "\n\n\n\n\n********************************************************"
puts "loadSource: $params(-path) doesn't exist"
puts "********************************************************\n\n\n\n\n"
exit -1
} else {
# Check the file extension
set fileExt [file extension $params(-path)]
if { ${fileExt} eq {.vhd} ||
${fileExt} eq {.vhdl}||
${fileExt} eq {.v} ||
${fileExt} eq {.vh} ||
${fileExt} eq {.sv} } {
# Update source file list
UpdateSrcFileLists $params(-path) ${lib}
} else {
puts "\n\n\n\n\n********************************************************"
puts "loadSource: $params(-path) does not have a \[.vhd,.vhdl,.v,.vh,.sv\] file extension"
puts "********************************************************\n\n\n\n\n"
exit -1
}
}
# Load all files from a directory
} elseif {$has_dir} {
# Check if directory doesn't exist
if { [file exists $params(-dir)] != 1 } {
puts "\n\n\n\n\n********************************************************"
puts "loadSource: $params(-dir) doesn't exist"
puts "********************************************************\n\n\n\n\n"
exit -1
} else {
# Get a list of all RTL files
set list ""
set list_rc [catch {
set list [glob -directory $params(-dir) *.vhd *.vhdl *.v *.vh *.sv]
} _RESULT]
# Load all the RTL files
if { ${list} != "" } {
foreach pntr ${list} {
# Update source file list
UpdateSrcFileLists ${pntr} ${lib}
}
} else {
puts "\n\n\n\n\n********************************************************"
puts "loadSource: $params(-dir) directory does not have any \[.vhd,.vhdl,.v,.vh,.sv,.dat,.coe,.mem,.edif,.dcp\] files"
puts "********************************************************\n\n\n\n\n"
exit -1
}
}
}
}
1 change: 1 addition & 0 deletions system_cadence_genus.mk
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ endif
export RUCKUS_GENUS_DIR = $(RUCKUS_DIR)/cadence/genus
export RUCKUS_PROC_TCL = $(RUCKUS_GENUS_DIR)/proc.tcl
export RUCKUS_QUIET_FLAG = -quiet
export RUCKUS_PROC_TCL_COMBO = $(RUCKUS_QUIET_FLAG) $(RUCKUS_PROC_TCL)

# Project Build Directory
export OUT_DIR = $(abspath $(TOP_DIR)/build/$(PROJECT))
Expand Down
9 changes: 5 additions & 4 deletions system_fabulous.mk
Original file line number Diff line number Diff line change
Expand Up @@ -44,9 +44,10 @@ endif
ifndef RUCKUS_DIR
export RUCKUS_DIR = $(MODULES)/ruckus
endif
export RUCKUS_DC_DIR = $(RUCKUS_DIR)/fabulous
export RUCKUS_PROC_TCL = $(RUCKUS_DC_DIR)/proc.tcl
export RUCKUS_FAB_DIR = $(RUCKUS_DIR)/fabulous
export RUCKUS_PROC_TCL = $(RUCKUS_FAB_DIR)/proc.tcl
export RUCKUS_QUIET_FLAG = -verbose
export RUCKUS_PROC_TCL_COMBO = $(RUCKUS_QUIET_FLAG) $(RUCKUS_PROC_TCL)

# Project Build Directory
export OUT_DIR = $(abspath $(TOP_DIR)/build/$(PROJECT))
Expand Down Expand Up @@ -133,15 +134,15 @@ proj: dir
.PHONY : bin
bin: proj
$(call ACTION_HEADER,"Fabulous: Generate the bitstream")
@cd $(TOP_DIR)/build; export DUMP_HDL=0; python3 $(PYFAB) -s $(RUCKUS_DC_DIR)/build.tcl $(PROJECT)
@cd $(TOP_DIR)/build; export DUMP_HDL=0; python3 $(PYFAB) -s $(RUCKUS_FAB_DIR)/build.tcl $(PROJECT)

###############################################################
#### Generate the eFPGA fabric ################################
###############################################################
.PHONY : fabric
fabric: proj
$(call ACTION_HEADER,"Fabulous: Generate the eFPGA fabric")
@cd $(TOP_DIR)/build; export DUMP_HDL=1; python3 $(PYFAB) -s $(RUCKUS_DC_DIR)/build.tcl $(PROJECT)
@cd $(TOP_DIR)/build; export DUMP_HDL=1; python3 $(PYFAB) -s $(RUCKUS_FAB_DIR)/build.tcl $(PROJECT)

###############################################################
#### Interactive Mode #######################################
Expand Down
1 change: 1 addition & 0 deletions system_synopsys_dc.mk
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,7 @@ endif
export RUCKUS_DC_DIR = $(RUCKUS_DIR)/synopsys/design_compiler
export RUCKUS_PROC_TCL = $(RUCKUS_DC_DIR)/proc.tcl
export RUCKUS_QUIET_FLAG = -verbose
export RUCKUS_PROC_TCL_COMBO = $(RUCKUS_QUIET_FLAG) $(RUCKUS_PROC_TCL)

ifndef PARALLEL_SYNTH
export PARALLEL_SYNTH = $(shell cat /proc/cpuinfo | grep processor | wc -l)
Expand Down
1 change: 1 addition & 0 deletions system_vivado.mk
Original file line number Diff line number Diff line change
Expand Up @@ -88,6 +88,7 @@ endif
export SOURCE_DEPEND = $(OUT_DIR)/$(PROJECT)_sources.txt
export RUCKUS_PROC_TCL = $(RUCKUS_DIR)/vivado/proc.tcl
export RUCKUS_QUIET_FLAG = -quiet
export RUCKUS_PROC_TCL_COMBO = $(RUCKUS_QUIET_FLAG) $(RUCKUS_PROC_TCL)

# Images Directory
export IMAGES_DIR = $(abspath $(PROJ_DIR)/images)
Expand Down

0 comments on commit d657b0a

Please sign in to comment.