Merge remote-tracking branch 'origin/pre-release' into i2c-dev

slaclab · Apr 17, 2024 · 4148108 · 4148108
2 parents f2eea94 + 5db1100
commit 4148108
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diff --git a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd
@@ -313,7 +313,12 @@ begin
                -- Start output when a block or end of frame is available
                elsif fifoValidLast = '1' or (VALID_THOLD_G /= 0 and fifoRdCount >= VALID_THOLD_G) then
                   fifoInFrame <= '1' after TPD_G;
+
+               -- Prevent the FIFO from locking up when frame deeper than what the U_Fifo can hold
+               elsif (fifoAFull = '1') then
+                  fifoInFrame <= '1' after TPD_G;
                end if;
+
             end if;
          end process;
 

diff --git a/tests/test_AxiStreamFifoV2IpIntegrator.py b/tests/test_AxiStreamFifoV2IpIntegrator.py
@@ -148,13 +148,20 @@ def incrementing_payload(length):
 ##############################################################################
 
 paramSweep = []
+# Sweep through different master/slave data sizes
 for sTdataByte in ['2','5','6']:
     for mTdataByte in ['2','5','6']:
         tmpDict = {
           "M_TDATA_NUM_BYTES": mTdataByte,
           "S_TDATA_NUM_BYTES": sTdataByte,
         }
         paramSweep.append(tmpDict)
+# Check for the case where the (VALID_THOLD_G=0) and AXI stream frame is buffer than the FIFO
+tmpDict = {
+  "VALID_THOLD": '0',
+  "FIFO_ADDR_WIDTH": '4',
+}
+paramSweep.append(tmpDict)
 
 ##############################################################################