code clean up

slaclab · Mar 26, 2024 · 52a0e87 · 52a0e87
1 parent b5ab962
commit 52a0e87
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/python/surf/xilinx/_AxiPciePhy.py b/python/surf/xilinx/_AxiPciePhy.py
@@ -271,11 +271,11 @@ def updateLinkStatus(self):
         if (self.CapabilitiesPointer.value() >= 0x40):
 
             # Go to the Capabilities Pointer offset and get the Capabilities Express Endpoint offset
-            offset = self.DevSpecRegion[self.CapabilitiesPointer.value()-0x40+1].get()
+            offset = self.DevSpecRegion[(self.CapabilitiesPointer.value()-0x40) + 1].get()
 
             # Capabilities Express Endpoint offset
-            linkStatus = self.DevSpecRegion[offset-0x40+ 0x12].get()
-            linkCap    = self.DevSpecRegion[offset-0x40+ 0x0C].get()
+            linkStatus = self.DevSpecRegion[(offset-0x40) + 0x12].get()
+            linkCap    = self.DevSpecRegion[(offset-0x40) + 0x0C].get()
 
             # Set the link speed and width status
             self.LnkStaSpeed.set( (linkStatus>>0) & 0xF )