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Add missing record element to initializers #1146

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Mar 26, 2024
Merged

Add missing record element to initializers #1146

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19 changes: 10 additions & 9 deletions devices/Nxp/Sc18Is602/rtl/Sc18Is602Core.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -24,14 +24,14 @@ use surf.I2cPkg.all;

entity Sc18Is602Core is
generic (
TPD_G : time := 1 ns;
I2C_BASE_ADDR_G : slv(2 downto 0) := "000"; -- A[2:0] pin config
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
SDO_MUX_SEL_MAP_G : Slv2Array(3 downto 0) := (0 => "00", 1 => "01", 2 => "10", 3 => "11");
ADDRESS_SIZE_G : IntegerArray(3 downto 0) := (others => 7); -- SPI Address bits per channel
DATA_SIZE_G : IntegerArray(3 downto 0) := (others => 16); -- SPI Data bits per channel
AXIL_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
TPD_G : time := 1 ns;
I2C_BASE_ADDR_G : slv(2 downto 0) := "000"; -- A[2:0] pin config
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
SDO_MUX_SEL_MAP_G : Slv2Array(3 downto 0) := (0 => "00", 1 => "01", 2 => "10", 3 => "11");
ADDRESS_SIZE_G : IntegerArray(3 downto 0) := (others => 7); -- SPI Address bits per channel
DATA_SIZE_G : IntegerArray(3 downto 0) := (others => 16); -- SPI Data bits per channel
AXIL_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
port (
-- I2C Ports
i2ci : in i2c_in_type;
Expand Down Expand Up @@ -90,7 +90,8 @@ architecture rtl of Sc18Is602Core is
regReq => '0',
busReq => '0',
endianness => '1', -- Big endian
repeatStart => '0');
repeatStart => '0',
wrDataOnRd => '0');

type StateType is (
IDLE_S,
Expand Down
11 changes: 6 additions & 5 deletions devices/Silabs/si5394/rtl/Si5394I2cCore.vhd
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Expand Up @@ -25,8 +25,8 @@ use surf.I2cPkg.all;
entity Si5394I2cCore is
generic (
TPD_G : time := 1 ns;
MEMORY_INIT_FILE_G : string := "none"; -- Used to initialization boot ROM
I2C_BASE_ADDR_G : slv(1 downto 0) := "00"; -- A[1:0] pin config
MEMORY_INIT_FILE_G : string := "none"; -- Used to initialization boot ROM
I2C_BASE_ADDR_G : slv(1 downto 0) := "00"; -- A[1:0] pin config
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
AXIL_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
Expand Down Expand Up @@ -84,7 +84,8 @@ architecture rtl of Si5394I2cCore is
regReq => '0',
busReq => '0',
endianness => '0',
repeatStart => '0');
repeatStart => '0',
wrDataOnRd => '0');

type StateType is (
POR_WAIT_S,
Expand Down Expand Up @@ -422,8 +423,8 @@ begin
generic map(
TPD_G => TPD_G,
DURATION_G => getTimeRatio(100.0E-9, (1.0/AXIL_CLK_FREQ_G)), -- min 100 ns pulse
IN_POLARITY_G => '1', -- active HIGH input
OUT_POLARITY_G => '0') -- active LOW output
IN_POLARITY_G => '1', -- active HIGH input
OUT_POLARITY_G => '0') -- active LOW output
port map (
clk => axilClk,
arst => axilRst,
Expand Down
17 changes: 9 additions & 8 deletions protocols/i2c/axi/AxiI2cEepromCore.vhd
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Expand Up @@ -36,13 +36,13 @@ use surf.I2cPkg.all;

entity AxiI2cEepromCore is
generic (
TPD_G : time := 1 ns;
ADDR_WIDTH_G : positive := 16;
POLL_TIMEOUT_G : positive := 16;
I2C_ADDR_G : slv(6 downto 0) := "1010000";
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
AXI_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
TPD_G : time := 1 ns;
ADDR_WIDTH_G : positive := 16;
POLL_TIMEOUT_G : positive := 16;
I2C_ADDR_G : slv(6 downto 0) := "1010000";
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
AXI_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
port (
-- I2C Ports
i2ci : in i2c_in_type;
Expand Down Expand Up @@ -82,7 +82,8 @@ architecture rtl of AxiI2cEepromCore is
regReq => '0',
busReq => '0',
endianness => '1', -- Big endian
repeatStart => '0');
repeatStart => '0',
wrDataOnRd => '0');

type StateType is (
IDLE_S,
Expand Down
3 changes: 2 additions & 1 deletion protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd
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Expand Up @@ -85,7 +85,8 @@ architecture mapping of AxiLiteCrossbarI2cMux is
regReq => '0',
busReq => '0',
endianness => DEVICE_MAP_C.endianness,
repeatStart => DEVICE_MAP_C.repeatStart);
repeatStart => DEVICE_MAP_C.repeatStart,
wrDataOnRd => '0');

type StateType is (
IDLE_S,
Expand Down
9 changes: 5 additions & 4 deletions protocols/pmbus/rtl/AxiLitePMbusMasterCore.vhd
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Expand Up @@ -116,7 +116,8 @@ architecture rtl of AxiLitePMbusMasterCore is
regReq => '0',
busReq => '0',
endianness => '0', -- Little endian
repeatStart => '1');
repeatStart => '1',
wrDataOnRd => '0');

type StateType is (
IDLE_S,
Expand Down Expand Up @@ -236,9 +237,9 @@ begin

-- Read back I2C configuration
if axilWriteMaster.awaddr(7 downto 0) = x"00" then
v.regIn.i2cAddr := axilWriteMaster.wData(9 downto 0);
v.regIn.tenbit := axilWriteMaster.wData(10);
v.ignoreResp := axilWriteMaster.wData(11);
v.regIn.i2cAddr := axilWriteMaster.wData(9 downto 0);
v.regIn.tenbit := axilWriteMaster.wData(10);
v.ignoreResp := axilWriteMaster.wData(11);
end if;

-- Send AXI-Lite response
Expand Down
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