Improve debuggability of selftest, expand AArch64 model #126
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This commit improves debuggability of the selftest by printing the input code, output code, and output registers in case of memory or register mismatch. Signed-off-by: Hanno Becker <[email protected]>
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This commit adds the parent class - VShiftImmediateBasic for the instructions `ushr` and `shl`, and - VShiftImmediateRounding for the instruction `srshr`. It also adds a new instruction `sshr` to the `VShiftImmediateBasic` category, and `urshr` to `VShiftImmediateComplex`. The motivation for those categories is that they feature in Arm's SWOGs: Most CPUs seem to have the same instruction characteristics for all of them, so having a parent class helps modelling.
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This commit improves debuggability of the selftest by printing the input code, output code, and output registers in case of memory or register mismatch.
This commit adds the parent class
for the instructions
ushrandshl, andfor the instruction
srshr.It also adds a new instruction
sshrto theVShiftImmediateBasiccategory, and
urshrtoVShiftImmediateComplex.The motivation for those categories is that they feature in Arm's SWOGs:
Most CPUs seem to have the same instruction characteristics for all of
them, so having a parent class helps modelling.