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Welcome to the CSE237D-PYNQ-SNN-Accelerator wiki!

Project Overview:

Spiking Neural Networks (SNN) are third generation neural networks gaining importance due to their similarity to biological neural systems. However, the real world engineering applications of SNNs have been limited due to the increased computational costs associated with these networks. It is important to accelerate their hardware implementation to enable widespread integration in smart embedded systems. This paper describes the implementation of such an SNN hardware accelerator on a System on Chip (pSoC) - has programmable logic and processor core. At each layer, computation involves multiply-accumulate and other matrix operations, for which the parallel architecture of the FPGA within SoC is well suited. The Spike Response Model (SRM) is the chosen neuron model wherein the information will be encoded in the timing between spikes. The accelerator implementation on PYNQ-Z1 board is aimed to provide a 20x speedup over an equivalent python software implementation for the MNIST image dataset. Performance improvement and strong scaling is expected to be attained through the efficient division of work between the processor and programmable logic in SoC. Our results will help indicate the suitability of the SRM model for large scale SNN hardware implementation.