fpga: Include SPI master during linting

Signed-off-by: Joachim Strömbergson <[email protected]>
tillitis · Nov 15, 2024 · 3a98f03 · 3a98f03
1 parent 6c0fc26
commit 3a98f03
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile
@@ -199,6 +199,7 @@ LINT_FLAGS = +1364-2005ext+ --lint-only \
 lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
 	$(LINT) $(LINT_FLAGS) \
 	-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
+	-DINCLUDE_SPI_MASTER \
 	-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
 	-DUDS_HEX=\"$(P)/data/uds.hex\" \
 	-DUDI_HEX=\"$(P)/data/udi.hex\" \