Rename files

hw/application_fpga/Makefile

@@ -79,8 +79,8 @@ FPGA_SRC = \
 
 # Verilator simulation specific source files.
 VERILATOR_FPGA_SRC = \
-	$(P)/tb/application_fpga_vsim.v \
-	$(P)/tb/reset_gen_vsim.v
+	$(P)/tb/application_fpga_sim.v \
+	$(P)/tb/reset_gen_sim.v
 
 # Common verilog source files.
 VERILOG_SRCS = \

hw/application_fpga/tb/application_fpga_vsim.v → hw/application_fpga/tb/application_fpga_sim.v

@@ -1,10 +1,10 @@
 //======================================================================
 //
-// application_fpga.v
-// ------------------
+// application_fpga_sim.v
+// ----------------------
 // Top level module of the application FPGA.
 // The design exposes a UART interface to allow a host to
-// send commands and receive resposes as needed load, execute and
+// send commands and receive responses as needed load, execute and
 // communicate with applications.
 //
 //

hw/application_fpga/tb/reset_gen_vsim.v → hw/application_fpga/tb/reset_gen_sim.v

@@ -1,6 +1,6 @@
 //======================================================================
 //
-// reset_gen_vsim.v
+// reset_gen_sim.v
 // ----------------
 // Reset generator Verilator simulation of the application_fpga.
 //