Merge the Cadence and Synopsys plugins into Hammer (#713)

* merge synopsys and cadence plugins into hammer

* get e2e tests working with asap7 on a machines

* add ICV link to docs

* incorporate genus retiming commit

* incorporate genus ILM blackboxes commit

* fix type error

* add defines for sky130 post-syn sim

* Update keys for sky130 at BWRC used for #740

* -top should be optional (#34)

* extraneous type:ignores with local mypy

* Revert "extraneous type:ignores with local mypy"

This reverts commit b0f5f95.

* openroad at bwrc moved to common location

---------

Co-authored-by: Harrison Liew <[email protected]>

.gitmodules

@@ -1,12 +1,4 @@
-[submodule "e2e/hammer-cadence-plugins"]
-	path = e2e/hammer-cadence-plugins
-	url = [email protected]:ucb-bar/hammer-cadence-plugins
-	branch = packaging
 [submodule "e2e/hammer-mentor-plugins"]
 	path = e2e/hammer-mentor-plugins
 	url = [email protected]:ucb-bar/hammer-mentor-plugins
-	branch = packaging
-[submodule "e2e/hammer-synopsys-plugins"]
-	path = e2e/hammer-synopsys-plugins
-	url = [email protected]:ucb-bar/hammer-synopsys-plugins
-	branch = packaging
+	branch = master

doc/CAD-Tools/ICV.md

@@ -0,0 +1 @@
+../../hammer/drc/icv/README.md

doc/CAD-Tools/index.rst

@@ -14,3 +14,4 @@ The package should contain an class object named 'tool' to create an instance of
    Hammer-CAD-Tools
    Tool-Plugin-Setup
    OpenROAD
+   ICV

e2e/.gitignore

@@ -1,2 +1,3 @@
 poetry.lock
 *.log
+obj_dir*

e2e/Makefile

@@ -0,0 +1 @@
+include obj_dir/hammer.d

e2e/README.md

@@ -1,31 +1,60 @@
 # Hammer End-to-End Integration Tests
 
-This folder contains an end-to-end (RTL -> GDS) smoketest flow using Hammer, using either of the OpenROAD or Cadence toolchains, and the ASAP7 or Skywater 130 PDKs.
+This folder contains an end-to-end (RTL -> GDS) smoketest flow using Hammer, using the Cadence toolchain, and the ASAP7 or Skywater 130 PDKs.
 
 ## Setup
 
-### Environment
+The integration tests use Hammer as a source dependency, so create the e2e poetry environment.
 
-This repo has environment configs (commercial CAD tool paths and license servers) for Berkeley EECS compute nodes (BWRC, Millennium, and instructional machines) in `env`.
-Add a file for your specific environment in `env` modeled after the provided files.
+```shell
+poetry install
+poetry shell
+```
 
-### PDKs
+We provide configs for Berkeley EECS compute nodes: BWRC (`-bwrc`), Millennium (`-a`), and instructional machines (`-inst`).
 
-#### ASAP7
+- Environment configs (commercial CAD tool paths and license servers) are in `env`
+- PDK configs for ASAP7 and sky130 (pointers to PDK paths and CAD tool versions) are in `pdks`
+- The common design config (which CAD tool plugins to use and the design input files) in `configs/common.yml`
+- The PDK specific design config (clock, placement, and pin constraints, and which SRAM generator to use) in `configs/{asap7,sky130}.yml`
 
-If you're using a Berkeley EECS compute node, find the ASAP7 install configs in `pdks/asap7-{a,bwrc,inst}.yml`.
+First, use Hammer to construct a Makefile fragment with targets for all parts of the RTL -> GDS flow.
+Specify the configs according to which PDK and environment you are using.
 
-If you're using another environment:
+```shell
+hammer-vlsi -e env/a-env.yml -p pdks/asap7-a.yml -p configs/common.yml -p configs/asap7.yml build
+```
 
-1. Clone the [asap7 repo](https://github.com/The-OpenROAD-Project/asap7)
-2. Create an ASAP7 install config modeled after the configs in `pdks/asap7{a,bwrc,inst}.yml`
+Hammer will generate a Makefile fragment in `obj_dir/hammer.d`.
 
-### CAD Tools
+### Run the Flow
 
-### Designs
+- RTL simulation
+    - `make sim-rtl HAMMER_EXTRA_ARGS="-p configs/sim.yml"`
+    - Generated waveform in `obj_dir/sim-rtl-rundir/output.fsdb`
+- Synthesis
+    - `make syn`
+    - Gate-level netlist in `obj_dir/syn-rundir/pass.mapped.v`
+- Post-Synthesis simulation
+    - `make syn-to-sim HAMMER_EXTRA_ARGS="-p configs/syn-sim.yml"`
+    - `make sim-syn HAMMER_EXTRA_ARGS="-p configs/syn-sim.yml"`
+    - Generated waveform and register forcing ucli script in `obj_dir/sim-syn-rundir`
+- PnR
+    - `make syn-to-par`
+    - `make par`
+    - LVS netlist (`pass.lvs.v`) and GDS (`pass.gds`) in `obj_dir/par-rundir`
+- Post-PnR simulation
+    - `make par-to-sim HAMMER_EXTRA_ARGS="-p configs/par-sim.yml"`
+    - `make sim-par HAMMER_EXTRA_ARGS="-p configs/par-sim.yml"`
 
-## Running Hammer
+### Custom Setups
 
-```shell
-hammer-vlsi -e env/a-env.yml -p pdks/asap7-a.yml -p test.yml
-```
+If you're not using a Berkeley EECS compute node, you can create your own environment setup.
+
+- Create an environment config for your node to specify the location of the CAD tools, modeled after the yaml files in `env`
+- Create a PDK config for your node to specify the PDK paths and versions, modeled after the yaml files in `pdks`
+- Point to your custom configs when running `hammer-vlsi`. The rest of the flow should be identical
+
+#### ASAP7 Install
+
+Clone the [asap7 repo](https://github.com/The-OpenROAD-Project/asap7) somewhere and reference the path in your PDK yaml config.

e2e/configs/test.yml → e2e/configs/asap7.yml

@@ -1,25 +1,9 @@
-# Generate Make include to aid in tlow
-vlsi.core.build_system: make
-
-vlsi.inputs.power_spec_type: "cpf"
-vlsi.inputs.power_spec_mode: "auto"
-
-synthesis.inputs:
-  top_module: "pass"
-  input_files: ["src/pass.v"]
-
 # Specify clock signals
 vlsi.inputs.clocks: [
   {name: "clock", period: "5ns", uncertainty: "0.1ns"}
 ]
 
 # Tool options.
-vlsi.core.synthesis_tool: "hammer.synthesis.genus"
-
-vlsi.core.par_tool: "hammer.par.innovus"
-par.innovus.design_flow_effort: "standard"
-par.inputs.gds_merge: true
-par.innovus.floorplan_mode: "generate"
 vlsi.inputs.placement_constraints:
   - path: "pass"
     type: toplevel
@@ -44,5 +28,6 @@ vlsi.inputs.delays: [
   {name: "out", clock: "clock", delay: "2", direction: "output"}
 ]
 
-vlsi.core.sim_tool: "hammer.sim.vcs"
-vlsi.core.power_tool: "hammer.power.voltus"
+
+# SRAM Compiler compiler options
+vlsi.core.sram_generator_tool: "hammer.technology.asap7.sram_compiler"

e2e/configs/common.yml

@@ -0,0 +1,22 @@
+# Generate Make include to aid in flow
+vlsi.core.build_system: make
+
+vlsi.inputs.power_spec_type: "cpf"
+vlsi.inputs.power_spec_mode: "auto"
+
+synthesis.inputs:
+  top_module: "pass"
+  input_files: ["src/pass.v"]
+
+vlsi.core.synthesis_tool: "hammer.synthesis.genus"
+
+vlsi.core.par_tool: "hammer.par.innovus"
+par.innovus.design_flow_effort: "standard"
+par.inputs.gds_merge: true
+par.innovus.floorplan_mode: "generate"
+
+vlsi.core.sim_tool: "hammer.sim.vcs"
+vlsi.core.timing_tool: "hammer.timing.tempus"
+vlsi.core.formal_tool: "hammer.formal.conformal"
+vlsi.core.drc_tool: "hammer.drc.calibre"
+vlsi.core.lvs_tool: "hammer.lvs.calibre"

e2e/configs/par-sim.yml

@@ -10,4 +10,3 @@ sim.inputs:
   options: ['-timescale=1ns/10ps']
   options_meta: append
   timing_annotated: false
-

e2e/configs/sky130-test.yml → e2e/configs/sky130.yml

@@ -1,26 +1,8 @@
-# Generate Make include to aid in flow
-vlsi.core.build_system: make
-
-vlsi.inputs.power_spec_type: "cpf"
-vlsi.inputs.power_spec_mode: "auto"
-
-synthesis.inputs:
-  top_module: "pass"
-  input_files: ["src/pass.v"]
-
 # Specify clock signals
 vlsi.inputs.clocks: [
   {name: "clock", period: "10ns", uncertainty: "0.1ns"}
 ]
 
-# Tool options.
-vlsi.core.synthesis_tool: "hammer.synthesis.genus"
-
-# Placement Constraints
-vlsi.core.par_tool: "hammer.par.innovus"
-par.innovus.design_flow_effort: "standard"
-par.inputs.gds_merge: true
-par.innovus.floorplan_mode: "generate"
 vlsi.inputs.placement_constraints:
   - path: "pass"
     type: toplevel
@@ -70,8 +52,5 @@ vlsi.inputs.delays: [
   {name: "out", clock: "clock", delay: "2", direction: "output"}
 ]
 
-vlsi.core.sim_tool: "hammer.sim.vcs"
-vlsi.core.power_tool: "hammer.power.voltus"
-
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"

e2e/configs/syn-sim.yml

@@ -10,4 +10,3 @@ sim.inputs:
   options: ['-timescale=1ns/10ps']
   options_meta: append
   timing_annotated: true
-

e2e/configs/voltus.yml

@@ -1,5 +1,6 @@
 # Voltus Power Analysis
 
+vlsi.core.power_tool: "hammer.power.voltus"
 power.inputs:
   level: "par"
   tb_name: "pass_tb"

e2e/pdks/asap7-a.yml

@@ -1,12 +1,12 @@
-vlsi.core.technology: asap7
+vlsi.core.technology: "hammer.technology.asap7"
 technology.asap7.pdk_install_dir: "/nscratch/asap7/asap7-master/asap7PDK_r1p7"
 technology.asap7.stdcell_install_dir: "/nscratch/asap7/asap7-master/asap7sc7p5t_27"
 
 synthesis.genus.version: "211"
 par.innovus.version: "211"
 
-sim.vcs.version: "S-2021.09-SP1-1"
-sim.vcs.verdi_home: "/ecad/tools/synopsys/verdi/${sim.vcs.version}"
+sim.vcs.version: "P-2019.06-SP1"
+sim.vcs.verdi_home: "/ecad/tools/synopsys/verdi/P-2019.06-SP2-2"
 sim.vcs.verdi_home_meta: lazysubst
 
 lvs.calibre.version: "2022.2_24.16"

e2e/pdks/sky130-a.yml

@@ -0,0 +1,17 @@
+vlsi.core.technology: "hammer.technology.sky130"
+technology.sky130:
+  sky130A: "/nscratch/vighneshiyer/miniconda3/envs/sky130/share/pdk/sky130A"
+  sram22_sky130_macros: "/nscratch/sky130/sram22_sky130_macros"
+  # sky130_nda:
+
+synthesis.genus.version: "211"
+par.innovus.version: "211"
+
+sim.vcs.version: "P-2019.06-SP1"
+sim.vcs.verdi_home: "/ecad/tools/synopsys/verdi/P-2019.06-SP2-2"
+sim.vcs.verdi_home_meta: lazysubst
+
+synthesis.yosys.yosys_bin: "/nscratch/vighneshiyer/miniconda3/envs/sky130/bin/yosys"
+par.openroad.openroad_bin: "/nscratch/vighneshiyer/miniconda3/envs/sky130/bin/openroad"
+drc.magic.magic_bin: "/nscratch/vighneshiyer/miniconda3/envs/sky130/bin/magic"
+lvs.netgen.netgen_bin: "/nscratch/vighneshiyer/miniconda3/envs/sky130/bin/netgen"

e2e/pdks/sky130-bwrc.yml

@@ -1,6 +1,7 @@
 vlsi.core.technology: "hammer.technology.sky130"
 technology.sky130:
-  sky130A: "/tools/commercial/skywater/local/sky130A"
+  sky130A: "/tools/commercial/skywater/local/chipyard-tutorial/.conda-sky130/share/pdk/sky130A"
+  sram22_sky130_macros: "/tools/commercial/skywater/local/chipyard-tutorial/sram22_sky130_macros"
   openram_lib: "/tools/commercial/skywater/local/sky130_sram_macros"
   sky130_nda: "/tools/commercial/skywater/swtech130/skywater-src-nda-20221031"
 
@@ -11,7 +12,12 @@ sim.vcs.version: "S-2021.09-SP1-1"
 sim.vcs.verdi_home: "/tools/synopsys/verdi/${sim.vcs.version}"
 sim.vcs.verdi_home_meta: lazysubst
 
-synthesis.yosys.yosys_bin: "/users/nayiri/conda/envs/yosys/bin/yosys"
-par.openroad.openroad_bin: "/users/nayiri/conda/envs/openroad/bin/openroad"
-drc.magic.magic_bin: "/tools/C/nayiri/installs/bin/magic"
-lvs.netgen.netgen_bin: "/tools/B/nayiri/installs/netgen/bin/netgen"
+synthesis.yosys.yosys_bin: "/tools/commercial/skywater/local/chipyard-tutorial/.conda-yosys/bin/yosys"
+par.openroad.openroad_bin: "/tools/commercial/skywater/local/chipyard-tutorial/.conda-openroad/bin/openroad"
+par.openroad.klayout_bin: "/tools/commercial/skywater/local/chipyard-tutorial/.conda-klayout/bin/klayout"
+drc.magic.magic_bin: "/tools/commercial/skywater/local/chipyard-tutorial/.conda-signoff/bin/magic"
+lvs.netgen.netgen_bin: "/tools/commercial/skywater/local/chipyard-tutorial/.conda-signoff/bin/netgen"
+
+# speed up tutorial runs & declutter log output
+par.openroad.timing_driven: false
+par.openroad.write_reports: false

e2e/pyproject.toml

@@ -10,8 +10,6 @@ repository = "https://github.com/ucb-bar/hammer"
 [tool.poetry.dependencies]
 python = "^3.9"
 hammer-vlsi = {path = "../.", extras = ["asap7"], develop = true}
-hammer-cadence-plugins = {path = "hammer-cadence-plugins", develop = true}
-hammer-synopsys-plugins = {path = "hammer-synopsys-plugins", develop = true}
 hammer-mentor-plugins = {path = "hammer-mentor-plugins", develop = true}
 
 [build-system]

e2e/src/pass_tb.v

@@ -3,11 +3,11 @@
 module pass_tb;
 
     reg clk = 0;
-    always #(5) clk = ~clk;
+    always #(20) clk = ~clk;
 
-    reg in; 
+    reg in;
     wire out;
-    
+
     pass pass_0 (
         .clock(clk),
         .in(in),
@@ -21,27 +21,27 @@ module pass_tb;
 
         in = 0;
         repeat(3) @(posedge clk);
-        
-        #1;
+
+        #5;
 
         in = 1;
-        
+
         if (out == 1) begin
             $display("***Test Failed***");
         end
 
         @(posedge clk);
-        #1;
+        #5;
 
         if (out == 0) begin
             $display("***Test Failed***");
         end
 
-        #1;
+        #5;
         in = 0;
 
         @(posedge clk);
-        #1;
+        #5;
 
         if (out == 1) begin
             $display("***Test Failed***");