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veripool · Jan 18, 2024 · 9105afa · 9105afa
1 parent 2a4294c
commit 9105afa
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/FAQ.rst b/FAQ.rst
@@ -951,6 +951,9 @@ common. Then add to your files:
    // verilog-typedef-regexp:"_t$"
    // End:
 
+Note in addition to the file using the AUTOs, any files which that file
+uses as submodules also need this.
+
 
 Why do the AUTOS ignore my ifdefs?
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