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Merge remote-tracking branch 'origin/dev-ext' into dev
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Dolu1990 committed Jan 14, 2025
2 parents 9906238 + 0bf034f commit 221ccfd
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Showing 3 changed files with 23 additions and 5 deletions.
2 changes: 1 addition & 1 deletion ext/SpinalHDL
Submodule SpinalHDL updated 44 files
+0 −2 build.sbt
+1 −1 core/src/main/scala/spinal/core/ClockDomain.scala
+13 −7 core/src/main/scala/spinal/core/Mem.scala
+12 −7 core/src/main/scala/spinal/core/MemBlackBox.scala
+2 −1 core/src/main/scala/spinal/core/Misc.scala
+12 −0 core/src/main/scala/spinal/core/Vec.scala
+1 −2 core/src/main/scala/spinal/core/internals/ComponentEmitter.scala
+13 −11 core/src/main/scala/spinal/core/internals/ComponentEmitterVerilog.scala
+6 −9 core/src/main/scala/spinal/core/internals/ComponentEmitterVhdl.scala
+119 −2 core/src/main/scala/spinal/core/internals/Phase.scala
+3 −2 core/src/main/scala/spinal/core/internals/Statement.scala
+4 −0 core/src/main/scala/spinal/core/sim/package.scala
+2 −0 lib/src/main/scala/spinal/lib/CrossClock.scala
+0 −3 lib/src/main/scala/spinal/lib/Mem.scala
+12 −8 lib/src/main/scala/spinal/lib/Stream.scala
+42 −13 lib/src/main/scala/spinal/lib/Utils.scala
+6 −7 lib/src/main/scala/spinal/lib/bus/amba3/apb/APB3.scala
+2 −2 lib/src/main/scala/spinal/lib/bus/amba4/axi/Axi4ToTilelink.scala
+2 −2 lib/src/main/scala/spinal/lib/bus/bmb/Bmb.scala
+37 −3 lib/src/main/scala/spinal/lib/bus/bmb/BmbDecoder.scala
+1 −1 lib/src/main/scala/spinal/lib/bus/misc/BusSlaveFactory.scala
+58 −46 lib/src/main/scala/spinal/lib/bus/regif/BusIf.scala
+1 −1 lib/src/main/scala/spinal/lib/bus/regif/BusInterface.scala
+32 −7 lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala
+2 −2 lib/src/main/scala/spinal/lib/com/usb/phy/UsbHubLsFs.scala
+3 −2 lib/src/main/scala/spinal/lib/cpu/riscv/debug/DebugModuleFiber.scala
+3 −2 lib/src/main/scala/spinal/lib/cpu/riscv/debug/DebugTransportModuleJtag.scala
+221 −0 lib/src/main/scala/spinal/lib/eda/TimingExtractor.scala
+0 −631 lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala
+0 −108 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022AbstractionDefinitionGenerator.scala
+0 −53 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022BusDefinitionGenerator.scala
+0 −262 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022ComponentGenerator.scala
+0 −55 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022DesignConfigXMLGenerator.scala
+0 −422 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022DesignXMLGenerator.scala
+0 −206 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022LogicalPart.scala
+0 −43 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACTGenerator.scala
+0 −427 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACTVivadoBusReference.scala
+0 −360 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACTVivadoComponentGenerator.scala
+95 −0 tester/src/test/scala/spinal/core/Apb3ConnectionTester.scala
+1 −0 tester/src/test/scala/spinal/lib/bus/regif/RegIfBasicAccessTester.scala
+29 −0 tester/src/test/scala/spinal/lib/bus/regif/RegIfDefaultErrorStateTester.scala
+55 −38 tester/src/test/scala/spinal/lib/bus/tilelink/CacheTester.scala
+0 −85 tester/src/test/scala/spinal/lib/tools/HDElkDiagramGenTester.scala
+0 −114 tester/src/test/scala/spinal/lib/tools/IPXACTGeneratorDemo.scala
6 changes: 4 additions & 2 deletions src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ object PrivilegedParam{
withUserTrap = false,
withRdTime = false,
withDebug = false,
mstatusFsInit = 0,
vendorId = 0,
archId = 46, //As spike
impId = 0,
Expand All @@ -53,6 +54,7 @@ case class PrivilegedParam(var withSupervisor : Boolean,
var withUserTrap: Boolean,
var withRdTime : Boolean,
var withDebug: Boolean,
var mstatusFsInit : Int,
var debugTriggers : Int,
var debugTriggersLsu : Boolean,
var vendorId: Int,
Expand Down Expand Up @@ -187,7 +189,7 @@ class PrivilegedPlugin(val p : PrivilegedParam, val hartIds : Seq[Int]) extends

bus.running := hartRunning
bus.halted := !hartRunning
bus.unavailable := BufferCC(ClockDomain.current.isResetActive)
bus.unavailable := BufferCC.withTag(ClockDomain.current.isResetActive)

when(debugMode) {
inhibateInterrupts(hartId)
Expand Down Expand Up @@ -519,7 +521,7 @@ class PrivilegedPlugin(val p : PrivilegedParam, val hartIds : Seq[Int]) extends
val status = new api.Csr(CSR.MSTATUS) {
val mie, mpie = RegInit(False)
val mpp = p.withUser.mux(RegInit(U"00"), U"11")
val fs = withFs generate RegInit(U"00")
val fs = withFs generate RegInit(U(p.mstatusFsInit, 2 bits))
val sd = False
val tsr, tvm = p.withSupervisor generate RegInit(False)
val tw = p.withUser.mux(RegInit(False), False)
Expand Down
20 changes: 18 additions & 2 deletions src/main/scala/vexiiriscv/test/VexiiRiscvProbe.scala
Original file line number Diff line number Diff line change
Expand Up @@ -99,6 +99,16 @@ class VexiiRiscvProbe(cpu : VexiiRiscv, kb : Option[konata.Backend], var withRvl
if(withRvls) rvls.jni.Frontend.deleteDisassemble(disass)
}

def clearStats(): Unit = {
for (hart <- harts) {
hart.jbStats.clear()
hart.branchStats.clear()
hart.commits = 0
}
statsCycleOffset = cycle
}

var statsCycleOffset = 0l
def getStats(): String = {
val str = new StringBuilder()
str ++= "### Stats ###\n"
Expand All @@ -119,8 +129,8 @@ class VexiiRiscvProbe(cpu : VexiiRiscv, kb : Option[konata.Backend], var withRvl
}

def cycleRatio(times: Long) = {
val rate = (1000f * times / cycle).toInt
f"${times}%7d / ${cycle}%7d ${rate / 10}%3d.${rate % 10}%%"
val rate = (1000f * times / (cycle-statsCycleOffset)).toInt
f"${times}%7d / ${cycle-statsCycleOffset}%7d ${rate / 10}%3d.${rate % 10}%%"
}

for ((hw, i) <- wbp.perf.dispatchFeedCounters.zipWithIndex) {
Expand All @@ -145,6 +155,12 @@ class VexiiRiscvProbe(cpu : VexiiRiscv, kb : Option[konata.Backend], var withRvl
var failed = 0l
var taken = 0l

def clear(): Unit = {
count = 0
failed = 0
taken = 0
}

override def toString(): String ={
val rate = (1000f*failed/count).toInt
val rate2 = (1000f*taken/count).toInt
Expand Down

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