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Refactoring of RTL MVAU/VVAU ops #977
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mmrahorovic
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Xilinx:refactor/rtl_integration
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Refactoring of RTL MVAU/VVAU ops #977
mmrahorovic
wants to merge
141
commits into
Xilinx:refactor/rtl_integration
from
mmrahorovic:refactor/mvu_vvu_rtl_op
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… and other minor changes
…d PyVerilator-related syntax change
…old layers to be by default true
…e_to_rtl transformation for MVU
Bugfix/fifo sizing tests
…ize multi-packed DSPs in MVU/VVU more efficiently
…o refactor/mvu_vvu_rtl_op
…default standalone_thresholds set to False
…g the ip and small fix to node execution
…stitched-ip method
…tions from pyverilator and method to wire in IP
…d-ip method and reverted default resType to LUT
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This PR is a clean-up of PR #963 where the Thresholding related changes have been excluded.
This PR introduces the RTL-based MVAU/VVAU custom-op. The test cases related to these custom-ops can be found here:
Depends on:
Note that this implies the RTL code is up-to-date with the double-pumping feature, but we will not support this in the FINN compiler flow and thus leave this flag unset. Main advantage is that we only need to maintain one RTL code-base instead of two different variants, since relatively significant changes/rework have been introduces as part of the double-pumped support.