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Refactoring of RTL MVAU/VVAU ops #977

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be1503a
First changes to custom_op for RTL-based MVAU
mmrahorovic Jan 3, 2023
8265985
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Apr 5, 2023
afab9cd
[rtl custom op]: initial implementation of mvu_8sx9
mmrahorovic Apr 6, 2023
a94fc3b
[rtl custom op]: testbench for mvu_8sx9
mmrahorovic Apr 6, 2023
98f9acc
[rtl custom op]: initial implementation of flow control component for…
mmrahorovic Apr 6, 2023
96925a9
[rtl custom op]: implementation of replay buffer for mvu
mmrahorovic Apr 6, 2023
a3d1156
[rtl custom op]: testbench for mvu_8sx9_axi (including axi_wrapper & …
mmrahorovic Apr 6, 2023
2aea664
[rtl custom op]: initial implementation of verilog wrapper for mvu_8s…
mmrahorovic Apr 6, 2023
c92e4e3
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Apr 6, 2023
8b57849
[rtl mvu]: fix tab indentation
mmrahorovic Apr 11, 2023
5e61f42
[rtl custom op]: fix to indentation
mmrahorovic Apr 12, 2023
cbee193
[rtl custom-op]: minor changes for compiler integration
mmrahorovic Apr 12, 2023
ba5e77b
[rtl custom op]: moved testbenches to separate directory
mmrahorovic Apr 12, 2023
69310b4
[rtl custom op]: fixed output width to ACCU_WIDTH
mmrahorovic Apr 12, 2023
cfcff00
[rtl custom op]: renamed file and added generic to switch between com…
mmrahorovic Apr 12, 2023
72b5196
[rtl custom op]: renamed file and added generic to switch between com…
mmrahorovic Apr 12, 2023
c068bb6
[rtl mvu]: added behavioral model DSP58
mmrahorovic May 8, 2023
18f94e7
[rtl mvu]: extended flow control wrapper with additional compute core…
mmrahorovic May 8, 2023
6d4a0a7
[rtl mvu]: fix to done_len flag when SIMD dimension fully unrolled an…
mmrahorovic May 8, 2023
90c547d
[rtl mvu tb]: updated testbench
mmrahorovic May 8, 2023
0c37f1f
[builder]: added specialize_to_rtl step and changed standalone thresh…
mmrahorovic May 8, 2023
5ccb016
[builder]: added specialize_to_rtl step
mmrahorovic May 8, 2023
f099f4b
[custom op]: added custom op MatrixVectorActivation_rtl
mmrahorovic May 8, 2023
9a3b0fd
[custom op]: added additional attribute to enable conversion to RTL (…
mmrahorovic May 8, 2023
38aa930
[custom op]: modified ip-stitching and code generation
mmrahorovic May 8, 2023
4e44934
[tests]: initial version of unit test for RTL custom op and specializ…
mmrahorovic May 8, 2023
cc361d9
[rtl mvu]: specialized compute core for 4-bit weights and activations…
mmrahorovic May 8, 2023
8eefb53
[rtl mvu]: specialized compute core for > 4-bit weights and activatio…
mmrahorovic May 8, 2023
e7109e7
[fpgadataflow transform]: initial specialize_to_rtl_layers-transform …
mmrahorovic May 8, 2023
d107b4d
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic May 9, 2023
5a868d1
[rtl mvu] fixes for latest memstream + linting
maltanar May 9, 2023
4a9cfa1
[rtl custom_op]: add support for external weights
mmrahorovic May 11, 2023
8a9ac1a
Specify clock and reset associations of bus interfaces.
preusser May 11, 2023
51bbe02
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic May 21, 2023
3d856b7
Merge branch 'dev' into feature/dsp_packing
preusser May 23, 2023
d9b9079
[rtlmvu] More fixes for memstream and param gen
maltanar May 15, 2023
a5f2a83
[Build] apply config to only FIFO nodes in step_set_fifo_depths
maltanar May 11, 2023
08cbdc5
Revised control interface attributes.
preusser May 24, 2023
48f0c5c
Merge branch 'dev' into feature/dsp_packing
preusser May 24, 2023
d058cc2
Mask device primitives from Verilator in favor of using behavioral code.
preusser May 24, 2023
a66f38f
[Deps] update qonnx
maltanar May 11, 2023
8f9bd04
Adding folding hints. Impl selection by case statement.
preusser May 24, 2023
8799707
Merge branch 'feature/verilator_workarounds' into feature/dsp_packing
preusser May 24, 2023
9de5ed6
Fixed behavioral sideband prediction.
preusser May 24, 2023
b6e92bb
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic May 24, 2023
239759a
[rtl mvu]: extension to allow selecting PE values that are not multip…
mmrahorovic May 24, 2023
8d3247c
[rtlmvu] Avoid unintentional verilator metacomments
maltanar May 24, 2023
ffc11d6
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic May 24, 2023
c866350
[rtl mvu]: extension to allow selecting PE values that are not multip…
mmrahorovic May 24, 2023
fd1e038
[rtl mvu axi]: updated comments on folding hints
mmrahorovic May 24, 2023
f60d4c6
[rtl custom op]: minor fixes to codegen
mmrahorovic Jun 2, 2023
a1ad304
[specialize-to-rtl]: add ram_style and rt_writeable_weights support
mmrahorovic Jun 2, 2023
2cbb68f
[rtllib]: change string type to parameter type due to Vivado error
mmrahorovic Jun 2, 2023
92eb0ed
[rtllib]: renamed variable for consistency
mmrahorovic Jun 2, 2023
471a221
Fix improper blocking assignment & linting.
preusser Jun 2, 2023
5c5dc09
[test rtl mvu]: modified/extended test cases
mmrahorovic Jun 2, 2023
b4eb9b6
[rtl mvu]: updated DSP58 >4-bit variant to lift SIMD%3==0 restriction
mmrahorovic Jun 30, 2023
ad63673
[rtl mvu]: bug fix for SIMD=1 init_leave_loads
mmrahorovic Jun 30, 2023
79e8a5e
[mvu rtl]: restrict index i to be less than 3 (within bounds of hi4)
mmrahorovic Jul 13, 2023
7be62b4
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Jul 17, 2023
e3493c3
Rewrite replay_buffer for input elasticity.
preusser Jun 2, 2023
44fae0c
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Jul 31, 2023
df51f11
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Aug 16, 2023
2efba68
[to-rtl]: Infer unique node names after transformation is applied
mmrahorovic Sep 5, 2023
114ea1b
[mvu rtl]: add synthesis directive to handle 'X in simulation
mmrahorovic Sep 18, 2023
79fafdb
[replay buffer rtl]: minor fix to when LEN=1 (= AWIDTH=0)
mmrahorovic Sep 18, 2023
619d9db
[mvu lut]: LUT-based MVU compute core
mmrahorovic Sep 18, 2023
090f2ac
[custom op]: add preferred_backend attribute
mmrahorovic Sep 19, 2023
ac5e82d
Ensure a minimum of two buffer slots even for length-1 sequences.
preusser Sep 21, 2023
d5ff2a2
Merge pull request #1 from Xilinx/bugfix/replay_len1
mmrahorovic Sep 21, 2023
bb94092
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic Sep 21, 2023
8515693
[rtl mvu wrapper]: support for vvu layer and rename
mmrahorovic Sep 21, 2023
cf28d78
[mvu vvu tb]: modified testbench to also support testing VVU on DSP58
mmrahorovic Sep 21, 2023
2617c39
[axi wrapper]: minor modification to comment description
mmrahorovic Sep 21, 2023
8ca5fe7
[mvu axi]: add support for VVU on DSP58
mmrahorovic Sep 21, 2023
32d6338
[mvu vvu axi]: renamed file for consistency purposes
mmrahorovic Sep 21, 2023
031406d
[mvu 8sx9]: added support for VVU on DSP58, resolved PyVerilator-caus…
mmrahorovic Sep 21, 2023
e2c1f15
[mvu vvu 8sx9]: renamed compute core for consistency
mmrahorovic Sep 21, 2023
adb5869
[axi wrapper]: changed parameter to localparam
mmrahorovic Sep 21, 2023
f54d438
[axi]: added support for LUT-based VVU
mmrahorovic Sep 21, 2023
a4e2ac7
[mvu vvu 8sx9]: minor change to list of generics
mmrahorovic Sep 21, 2023
40ad0b4
[mvu lut]: added support for VVU
mmrahorovic Sep 21, 2023
30fcb5b
[mvu vvu lut]: renamed file for consistency
mmrahorovic Sep 21, 2023
cb43438
Revert to proper address truncation without generation bit.
preusser Sep 21, 2023
b4b69f3
remove deletd/renamed files
mmrahorovic Sep 21, 2023
14c5fa9
[mvu vvu 8sx9]: renamed for consistency
mmrahorovic Sep 21, 2023
3a37588
[mvu vvu axi]: changes for renamed module
mmrahorovic Sep 21, 2023
afe36ba
[mvu vvu wrapper]: convert localparam to param
mmrahorovic Sep 25, 2023
e4f2f9e
[mvau-rtl custom-op]: bugfix to instantiate memstreamer, modified ren…
mmrahorovic Sep 25, 2023
b49b79a
[specialize to rtl]: fix to changed attribute name and added support …
mmrahorovic Sep 25, 2023
9bdba03
Adding core for DSP48 backport.
preusser Sep 19, 2023
2cf1ef7
[mvu rtl core]: added support for signed activations for DSP48-based …
mmrahorovic Sep 25, 2023
ab8d4a8
[rtl mvu custom-op]: add upper bound to SEGMENTLEN equal to number of…
mmrahorovic Sep 25, 2023
5a429fc
[mvu_vvu dsp58]: change weight input to 2D instead of 3D array
mmrahorovic Oct 13, 2023
a4a18bb
[mvu_vvu axi]: re-wire weights appropriately for VVU DSP58
mmrahorovic Oct 13, 2023
cc0737b
[mvu_vvu axi wrapper]: fix to IS_MVU parameter
mmrahorovic Oct 13, 2023
c0eff0b
[mvu_vvu tb]: WIP -- changes to self-checker and shape of input data
mmrahorovic Oct 13, 2023
cf7f494
[mvu vvu axi]: minor bugfixes to enable VVU
mmrahorovic Nov 1, 2023
5ffc221
[mvu vvu axi]: minor fix -- define mvauin_weight_t
mmrahorovic Nov 20, 2023
d573043
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Nov 27, 2023
40d652c
[rtl mvu op]: minor fix to chain length estimation and enabled behavi…
mmrahorovic Nov 29, 2023
6e98bac
[rtlsim]: use pyverilator util functions
mmrahorovic Dec 13, 2023
5dd74ad
[mvu vvu axi]: sign extend output tdata (byte-aligned)
mmrahorovic Dec 8, 2023
b20410b
[mvu core]: dsp48 convert unpacked array to packed array to work arou…
mmrahorovic Jan 8, 2024
1c2cc0c
[mvu axi]: update list of deduced parameters
mmrahorovic Jan 8, 2024
eeb3cea
[mvu custom-op]: remove lut-based implementation and update compute c…
mmrahorovic Jan 8, 2024
0813d14
[mvu axi]: remove LUT-based compute core
mmrahorovic Jan 8, 2024
4892d66
[hls custom-op]: enable reset in sim
mmrahorovic Jan 11, 2024
44f6e0f
[test mvu rtl]: updated test flow (DSP58 only)
mmrahorovic Jan 11, 2024
9b2cceb
[mvu vvu axi]: reworked flow control and backpressure handling by tpr…
mmrahorovic Jan 11, 2024
ee9f027
Adding DSP48E1 support for 8-bit compute. Todo: finer core differenti…
preusser Jan 31, 2024
3ab8296
Adding DSP48E1 support for 4-bit compute. Todo: finer core differenti…
preusser Jan 31, 2024
23c3f82
[Tests] Temporarily re-enable SWG exception for bnn_w2_a2_cnv_Pynq-Z1…
Jan 31, 2024
562d153
[Tests] Fix fpgadataflow split large fifos test
Jan 31, 2024
a884e11
Fix linting
Jan 31, 2024
f2424e7
Merge pull request #969 from Xilinx/bugfix/fifo_sizing_tests
auphelia Jan 31, 2024
bcd72ad
[mvu vvu axi]: minor bugfixes to enable VVU
mmrahorovic Nov 1, 2023
b116733
[mvu tb]: created separate vvu testbench and renamed mvu_vvu_axi tb
mmrahorovic Nov 1, 2023
e1f8db1
[mvu vvu axi]: minor fix -- define mvauin_weight_t
mmrahorovic Nov 20, 2023
88da696
[folding]: first attempt to extend folding transformation to parallel…
mmrahorovic Nov 20, 2023
a43c731
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing_vvu
mmrahorovic Feb 7, 2024
1814ea0
[mvu axi]: update list of deduced parameters
mmrahorovic Jan 8, 2024
f939c3e
[mvu vvu axi]: reworked flow control and backpressure handling by tpr…
mmrahorovic Jan 11, 2024
ef12de1
[mvu/vvu axi]: picked out modifications from another branch to enable…
mmrahorovic Feb 6, 2024
3d49ab5
[mvu test]: cleaned up test
mmrahorovic Feb 6, 2024
105ae6f
Revised control interface attributes.
preusser May 24, 2023
936ef69
[rtl mvu]: extension to allow selecting PE values that are not multip…
mmrahorovic May 24, 2023
9bf7e33
Starting on pumped DSP compute.
preusser Sep 29, 2023
80a5510
pulled latest changes related to double-pumping
mmrahorovic Feb 8, 2024
289749b
minor fix to param
mmrahorovic Feb 8, 2024
66f1b1a
Merge remote-tracking branch 'origin/feature/mvu_vvu_dsp_pumping' int…
mmrahorovic Feb 8, 2024
b51837b
added RTL-based MVAU and VVAU custom-ops
mmrahorovic Feb 7, 2024
86465e0
[builder]: renamed specialize_to_rtl step to specialize_layers step, …
mmrahorovic Feb 7, 2024
c8b793c
[builder]: added first version of specialize_layer step
mmrahorovic Feb 7, 2024
79ff911
pulled latest changes
mmrahorovic Feb 8, 2024
3f9e85c
fixed broken merge
mmrahorovic Feb 8, 2024
1245763
[mvau hls]: added lut/dsp estimation functions, function for stitchin…
mmrahorovic Feb 8, 2024
9a4dd04
[hwcustom op]: removed do_reset flag
mmrahorovic Feb 8, 2024
30f6ddf
[mvau hw-op]: moved lut/dsp estimations to specialized ops, modified …
mmrahorovic Feb 8, 2024
12ad48c
[hls mvau]: fixed cppsim bipolar activations, added call to util func…
mmrahorovic Feb 13, 2024
3202dc1
[hw mvau]: fixed bug for executing 2D arrays, modified create-stitche…
mmrahorovic Feb 13, 2024
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494 changes: 494 additions & 0 deletions finn-rtllib/mvu/mvu_4sx4u.sv

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492 changes: 492 additions & 0 deletions finn-rtllib/mvu/mvu_8sx8u_dsp48.sv

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93 changes: 93 additions & 0 deletions finn-rtllib/mvu/mvu_8sx9_axi_wrapper.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,93 @@
/******************************************************************************
* Copyright (C) 2022, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* @brief Verilog AXI-lite wrapper for MVU.
*****************************************************************************/

module $MODULE_NAME_AXI_WRAPPER$ #(
parameter MW = $MW$,
parameter MH = $MH$,
parameter PE = $PE$,
parameter SIMD = $SIMD$,
parameter ACTIVATION_WIDTH = $ACTIVATION_WIDTH$,
parameter WEIGHT_WIDTH = $WEIGHT_WIDTH$,
parameter ACCU_WIDTH = $ACCU_WIDTH$,
parameter SIGNED_ACTIVATIONS = $SIGNED_ACTIVATIONS$,
parameter SEGMENTLEN = $SEGMENTLEN$,
parameter RAM_STYLE = "$IBUF_RAM_STYLE$",

// Safely deducible parameters
parameter WEIGHT_STREAM_WIDTH_BA = (PE*SIMD*WEIGHT_WIDTH+7)/8 * 8,
parameter INPUT_STREAM_WIDTH_BA = (SIMD*ACTIVATION_WIDTH+7)/8 * 8,
parameter OUTPUT_LANES = PE,
parameter OUTPUT_STREAM_WIDTH_BA = (OUTPUT_LANES*ACCU_WIDTH + 7)/8 * 8
)(
// Global Control
(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axis_weights:s_axis_input:m_axis_output, ASSOCIATED_RESET ap_rst_n" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input ap_clk,
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
input ap_rst_n,

// Weight Stream
input [WEIGHT_STREAM_WIDTH_BA-1:0] s_axis_weights_tdata,
input s_axis_weights_tvalid,
output s_axis_weights_tready,

// Input Stream
input [INPUT_STREAM_WIDTH_BA-1:0] s_axis_input_tdata,
input s_axis_input_tvalid,
output s_axis_input_tready,

// Output Stream
output [OUTPUT_STREAM_WIDTH_BA-1:0] m_axis_output_tdata,
output m_axis_output_tvalid,
input m_axis_output_tready
);

mvu_8sx9_axi #(
.MW(MW), .MH(MH), .PE(PE), .SIMD(SIMD), .ACTIVATION_WIDTH(ACTIVATION_WIDTH),
.WEIGHT_WIDTH(WEIGHT_WIDTH), .ACCU_WIDTH(ACCU_WIDTH), .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS),
.SEGMENTLEN(SEGMENTLEN), .RAM_STYLE(RAM_STYLE)
) inst (
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.s_axis_weights_tdata(s_axis_weights_tdata),
.s_axis_weights_tvalid(s_axis_weights_tvalid),
.s_axis_weights_tready(s_axis_weights_tready),
.s_axis_input_tdata(s_axis_input_tdata),
.s_axis_input_tvalid(s_axis_input_tvalid),
.s_axis_input_tready(s_axis_input_tready),
.m_axis_output_tdata(m_axis_output_tdata),
.m_axis_output_tvalid(m_axis_output_tvalid),
.m_axis_output_tready(m_axis_output_tready)
);

endmodule : $MODULE_NAME_AXI_WRAPPER$
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