Verilog improvements. #1828
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Verilog improvements. #1828
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Owner
enjoy-digital
commented
Nov 6, 2023
enjoy-digital
commented
- Improve/Refactor namer.py.
- Use DUID in ClockDomainCrossing for deterministic generation.
…se_number/_build_pnd_for_group and add comments.
…erarchy_tree complexity.
…name and update_name_dict_with_group.
… to allow deterministic builds.
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