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Verilog improvements. #1828

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merged 18 commits into from
Nov 7, 2023
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1e805a8
fhdl/namer: Remove debug and add docstring comments.
enjoy-digital Nov 6, 2023
6214aa6
gen/fhdl/namer: Simplify _build_tree and add comments.
enjoy-digital Nov 6, 2023
d28b7a1
gen/fhdl/namer: Simplify _set_use_name/_build_pnd_from_tree and add c…
enjoy-digital Nov 6, 2023
36e4705
gen/fhdl/namer: Simplify _invert_pnd/_list_conflicting_signals/_set_u…
enjoy-digital Nov 6, 2023
a65d471
gen/fhdl/namer: Simplify _invert_pnd_build_signal_groups/_build_pnd a…
enjoy-digital Nov 6, 2023
9548259
gen/fhdl/namer: Simplify build_namespace and add comments.
enjoy-digital Nov 6, 2023
19a3ab2
gen/fhdl/namer: Improve class/variable names.
enjoy-digital Nov 6, 2023
16804ac
gen/fhdl/namer: Add update_hierarchy_node function to reduce build_hi…
enjoy-digital Nov 6, 2023
0efccae
gen/fhdl/namer: Simplify/Remove some redundancies.
enjoy-digital Nov 6, 2023
c005767
gen/fhdl/namer: Split build_signal_name_dict with build_hierarchical_…
enjoy-digital Nov 6, 2023
c8a96b8
gen/fhdl/namer: Add update method to HierarchyNode to replace update_…
enjoy-digital Nov 6, 2023
3df23a2
gen/fhdl/namer: Avoid deep level of nesting on build_signal_name_dict…
enjoy-digital Nov 6, 2023
9ce2922
gen/fhdl/namer: Add all_numbers to HierarchyNode to avoid hasattr use.
enjoy-digital Nov 6, 2023
af508fd
gen/fhdl/namer: Improve/Simplify SignalNamespace.get_name method.
enjoy-digital Nov 6, 2023
ef4235a
gen/fhdl/namer: Use _ for private functions and remove build_namespace.
enjoy-digital Nov 6, 2023
33fd774
interconnect/stream/ClockDomainCrossing: Use DUID for clock_domain id…
enjoy-digital Nov 6, 2023
5b989bc
gen/fhdl/verilog: Switch Assign/Operator types to IntEnum.
enjoy-digital Nov 6, 2023
657252c
gen/fhdl/namer: Update copyrights.
enjoy-digital Nov 6, 2023
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