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fix: TCLKA and TCLKB and EVRU/EVRD clocks. #94

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Oct 26, 2023
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16 changes: 9 additions & 7 deletions evrMrmApp/src/drvem.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -286,11 +286,6 @@ try{

} else if(formfactor==formFactor_mTCA) {

// mapping to TCLKA and TCLKB as UNIV16, 17
// we move down to UNIV0, 1
outputs[std::make_pair(OutputFPUniv,0)]=new MRMOutput(SB()<<n<<":FrontUnivOut0", this, OutputFPUniv, 16);
outputs[std::make_pair(OutputFPUniv,1)]=new MRMOutput(SB()<<n<<":FrontUnivOut1", this, OutputFPUniv, 17);

Comment on lines -289 to -293
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If this is removed, where is the configuration of TCLKA and TCLKB done on the MTCA EVR?

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I found the solution to my answer above in the pull request #95 and commit 64b5763, where the number of UNIV-IOs is extended to 18 and the TCLKA and TCLKB are mapped as UNIV-IO16 and 17.

Now I only have a question how this will be handled on the GUI.

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$(P)Out-TCLKA-Pat-Low00_15-SP etc.

shortcmls.resize(2);
shortcmls[0]=new MRMCML(n+":CML0", 0,*this,MRMCML::typeCML,form);
shortcmls[1]=new MRMCML(n+":CML1", 1,*this,MRMCML::typeCML,form);
Expand Down Expand Up @@ -685,7 +680,7 @@ EVRMRM::setSourceTS(TSSource src)
switch(src){
case TSSourceInternal:
// div!=0 selects src internal
div=(epicsUInt16)(eclk/clk);
div=roundToUInt(eclk/clk, 0xffff);
break;
case TSSourceEvent:
BITCLR(NAT,32, base, Control, Control_tsdbus);
Expand Down Expand Up @@ -727,7 +722,14 @@ EVRMRM::clockTSSet(double clk)
TSSource src=SourceTS();
double eclk=clock();

if(clk>eclk*1.01 || clk==0.0)
/* There is an issue with this and the embedded EVRs of the mTCA EVM vers
* 280b0207. The register holding the fractional synthesizer configuration
* word is empty, so eclk always resolves to 0, and so does clk. This messes
* up with the delay generators width/delay settings. By removing this check
* clockTS() can be used for the calculation of the width/delay.
* if(clk>eclk*1.01 || clk==0.0)
*/
if(clk==0.0)
clk=eclk;

SCOPED_LOCK(evrLock);
Expand Down
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