quick hack to get MMC0 to work on primer 25k (helloworld / nes15)

src/cart.sv

@@ -61,6 +61,23 @@ tri0 [21:0] prg_addr_b, chr_addr_b;
 tri0 [15:0] flags_out_b, audio_out_b;
 tri1 [7:0] prg_dout_b, chr_dout_b;
 
+// nand2mario: signals have to be declared first for gowin synthesis
+wire [15:0] ss5b_audio;
+wire [15:0] n163_audio;
+wire [7:0] n163_data;
+wire [5:0] exp_audioe;
+wire [15:0] mmc5_audio;
+wire [7:0] mmc5_data;
+wire [15:0] fds_audio;
+wire [7:0] fds_data;
+wire [15:0] vrc7_audio;
+wire [15:0] vrc6_audio;
+
+reg [6:0] prg_mask;
+reg [6:0] chr_mask;
+reg [1023:0] me;
+reg [9:0] mapper_en;
+
 // This mapper used to be default if no other mapper was found
 // It seems MMC0 is handled by map28. Does it have any purpose?
 // flags_out_b will be high if no other mappers are selected, so we use that.
@@ -127,7 +144,10 @@ MMC1 mmc1(
 // Notes  : This mapper relies on open bus and bus conflict behavior.          //
 // Games  : Donkey Kong                                                        //
 //*****************************************************************************//
-wire mapper28_en = me[0] | me[2] | me[3] | me[7] | me[94] | me[97] | me[180] | me[185] | me[28];
+wire mapper28_en /* synthesis syn_keep=1 */;
+// assign mapper28_en = (mapper_en == 0) | me[0] | me[2] | me[3] | me[7] | me[94] | me[97] | me[180] | me[185] | me[28];
+assign mapper28_en = 1;
+wire prg_allow_28 = prg_ain[15] && !prg_write;
 Mapper28 map28(
 	.clk        (clk),
 	.ce         (ce),
@@ -139,7 +159,8 @@ Mapper28 map28(
 	.prg_write  (prg_write),
 	.prg_din    (prg_din),
 	.prg_dout_b (prg_dout_b),
-	.prg_allow_b(prg_allow_b),
+	// .prg_allow(prg_allow_28),
+	.prg_allow_b(),
 	.chr_ain    (chr_ain),
 	.chr_aout_b (chr_addr_b),
 	.chr_read   (chr_read),
@@ -1726,7 +1747,6 @@ tri0 [1:0] fds_diskside_auto;
 // Notes  : Uses Mapper 31.15 (submapper) for NSF Player; NSF 1.0 only         //
 // Games  : Famicompo Pico 2014, NSF 1.0                                       //
 //*****************************************************************************//
-wire [5:0] exp_audioe;
 NSF nsfplayer(
 	.clk        (clk),
 	.ce         (ce),
@@ -1759,7 +1779,6 @@ NSF nsfplayer(
 	.fds_din    (fds_data)
 );
 
-wire [15:0] ss5b_audio;
 SS5b_mixed snd_5bm (
 	.clk(clk),
 	.ce(ce),
@@ -1771,8 +1790,6 @@ SS5b_mixed snd_5bm (
 	.audio_out(ss5b_audio)
 );
 
-wire [15:0] n163_audio;
-wire [7:0] n163_data;
 namco163_mixed snd_n163 (
 	.clk(clk),
 	.ce(ce),
@@ -1786,8 +1803,6 @@ namco163_mixed snd_n163 (
 	.audio_out(n163_audio)
 );
 
-wire [15:0] mmc5_audio;
-wire [7:0] mmc5_data;
 mmc5_mixed snd_mmc5 (
 	.clk(clk),
 	.ce(ce),
@@ -1801,8 +1816,6 @@ mmc5_mixed snd_mmc5 (
 	.audio_out(mmc5_audio)
 );
 
-wire [15:0] fds_audio;
-wire [7:0] fds_data;
 // fds_mixed snd_fds (
 // 	.clk(clk),
 // 	.ce(ce),
@@ -1815,7 +1828,6 @@ wire [7:0] fds_data;
 // 	.audio_out(fds_audio)
 // );
 
-wire [15:0] vrc7_audio;
 //vrc7_mixed snd_vrc7 (
 //	.clk(clk),
 //	.ce(ce),
@@ -1827,7 +1839,6 @@ wire [15:0] vrc7_audio;
 //	.audio_out(vrc7_audio)
 //);
 
-wire [15:0] vrc6_audio;
 //vrc6_mixed snd_vrc6 (
 //	.clk(clk),
 //	.ce(ce),
@@ -1841,14 +1852,11 @@ wire [15:0] vrc6_audio;
 //);
 
 
-reg [6:0] prg_mask;
-reg [6:0] chr_mask;
-reg [1023:0] me;
-
 always @* begin
 	me = 1023'd0;
 	me[{flags[18:17],flags[7:0]}] = 1'b1;
-
+	mapper_en = {flags[18:17],flags[7:0]};
+
 	case(flags[10:8])
 		0: prg_mask = 7'b0000000;
 		1: prg_mask = 7'b0000001;
@@ -1875,6 +1883,9 @@ always @* begin
 	{prg_aout,   prg_allow,   chr_aout,   vram_a10,   vram_ce,   chr_allow,   prg_dout,   chr_dout,   irq,   audio} =
 	{prg_addr_b, prg_allow_b, chr_addr_b, vram_a10_b, vram_ce_b, chr_allow_b, prg_dout_b, chr_dout_b, irq_b, audio_out_b};
 
+	prg_allow = mapper28_en ? prg_allow_28:
+				0;
+
 	// Currently only used for Mapper 16 EEPROM. Expand if needed.
 	{mapper_addr, mapper_data_out, mapper_prg_write, mapper_ovr} = (me[159] | me[16]) ?
 		{map16_mapper_addr, map16_data_out, map16_prg_write, map16_ovr} : 28'd0;

src/game_loader.v

@@ -37,15 +37,15 @@ assign mem_write = (((bytes_left != 0) && (state == S_LOADPRG || state == S_LOAD
                     || (downloading && (state == S_LOADHEADER || state == S_LOADFDS || state == S_LOADNSFH || state == S_LOADNSFD))) && indata_clk)
                     || ((bytes_left != 0) && ((state == S_CLEARRAM) || (state == S_COPYBIOS) || (state == S_COPYPLAY)) && clearclk == 4'h2);
 
-wire [2:0] prg_size = prgrom <= 1  ? 3'd0 :			// 16KB
+wire [2:0] prg_size /* synthesis syn_keep=1 */= prgrom <= 1  ? 3'd0 :			// 16KB
                       prgrom <= 2  ? 3'd1 : 		// 32KB
                       prgrom <= 4  ? 3'd2 : 		// 64KB
                       prgrom <= 8  ? 3'd3 : 		// 128KB
                       prgrom <= 16 ? 3'd4 : 		// 256KB
                       prgrom <= 32 ? 3'd5 : 		// 512KB
                       prgrom <= 64 ? 3'd6 : 3'd7;// 1MB/2MB
 
-wire [2:0] chr_size = chrrom <= 1  ? 3'd0 : 		// 8KB
+wire [2:0] chr_size /* synthesis syn_keep=1 */= chrrom <= 1  ? 3'd0 : 		// 8KB
                       chrrom <= 2  ? 3'd1 : 		// 16KB
                       chrrom <= 4  ? 3'd2 : 		// 32KB
                       chrrom <= 8  ? 3'd3 : 		// 64KB
@@ -65,7 +65,7 @@ wire is_dirty = !is_nes20 && ((ines[9][7:1] != 0)
                            || (ines[15] != 0));
 
 // Read the mapper number
-wire [7:0] mapper = {is_dirty ? 4'b0000 : ines[7][7:4], ines[6][7:4]};
+wire [7:0] mapper /* synthesis syn_keep=1 */ = {is_dirty ? 4'b0000 : ines[7][7:4], ines[6][7:4]};
 wire [7:0] ines2mapper = {is_nes20 ? ines[8] : 8'h00};
 wire [3:0] prgram = {is_nes20 ? ines[10][3:0] : 4'h0};
 wire [3:0] prg_nvram = (is_nes20 ? ines[10][7:4] : 4'h0);

src/mappers/Sunsoft.sv

@@ -98,7 +98,7 @@ end else if (ce) begin
 	end
 end
 
-always begin
+always @* begin
 	casez(mirroring[1:0])
 		2'b00: vram_a10 = {chr_ain[10]};    // vertical
 		2'b01: vram_a10 = {chr_ain[11]};    // horizontal
@@ -109,7 +109,7 @@ end
 reg [4:0] prgout;
 reg [7:0] chrout;
 
-always begin
+always @* begin
 	casez(prg_ain[15:13])
 		3'b011: prgout = prg_bank[0];
 		3'b100: prgout = prg_bank[1];
@@ -145,6 +145,8 @@ module SS5b_mixed (
 	output [15:0] audio_out
 );
 
+wire [15:0] exp_out;
+
 SS5b_audio snd_5b (
 	.clk(clk),
 	.ce(ce),
@@ -160,7 +162,6 @@ SS5b_audio snd_5b (
 // The expansion audio is much louder than APU audio, so we reduce it to 68% prior to
 // mixing.
 
-wire [15:0] exp_out;
 wire [15:0] exp_adj = (|exp_out[15:14] ? 16'hFFFF : {exp_out[13:0], exp_out[1:0]});
 wire [16:0] audio_mix = audio_in + (exp_adj + exp_adj[15:1]);
 
@@ -423,7 +424,7 @@ end else if (ce) begin
 		irq <= 1'b0; // IRQ ACK
 end
 
-always begin
+always @* begin
 	casez({mirroring})
 		2'b00   :   vram_a10 = {chr_ain[10]};    // vertical
 		2'b01   :   vram_a10 = {chr_ain[11]};    // horizontal
@@ -432,15 +433,15 @@ always begin
 end
 
 reg [7:0] prgsel;
-always begin
+always @* begin
 	case(prg_ain[14])
 	1'b0: prgsel = prg_bank_0;                // $8000 is swapable
 	1'b1: prgsel = mapper190 ? 8'h00 : 8'hFF; // $C000 is hardwired to first/last bank
 	endcase
 end
 
 reg [7:0] chrsel;
-always begin
+always @* begin
 	casez(chr_ain[12:11])
 		0: chrsel = chr_bank_0;
 		1: chrsel = chr_bank_1;
@@ -549,7 +550,7 @@ assign prg_aout = prg_is_ram ? prg_ram : {4'b00_00, prgout, prg_ain[13:0]};
 assign prg_allow = (prg_ain[15] && !prg_write) || (prg_is_ram && ram_enable);
 
 reg [6:0] chrout;
-always begin
+always @* begin
 	casez(chr_ain[12:11])
 		0: chrout = chr_bank_0;
 		1: chrout = chr_bank_1;
@@ -558,7 +559,7 @@ always begin
 	endcase
 end
 
-always begin
+always @* begin
 	casez(mirroring[1:0])
 		2'b00: vram_a10 = {chr_ain[10]};    // vertical
 		2'b01: vram_a10 = {chr_ain[11]};    // horizontal

src/mappers/generic.sv

@@ -178,7 +178,7 @@ always @(posedge clk) begin
 	end
 end
 
-always begin
+always @* begin
 	// mirroring mode
 	casez({flags[16], flags[14]})
 		3'b00   :   vram_a10 = chr_ain[11];    // horizontal
@@ -452,7 +452,7 @@ end else if (ce) begin
 end
 
 reg [3:0] prgout;
-always begin
+always @* begin
 	casez({prg_ain[14], mapper232})
 		2'b0?: prgout = prg_bank;
 		2'b10: prgout = 4'b1111;
@@ -530,7 +530,7 @@ always @(posedge clk) begin
 	end
 end
 
-always begin
+always @* begin
 	vram_a10 = {chr_ain[10]};    // four screen (consecutive)
 end
 
@@ -619,7 +619,7 @@ assign vram_ce = chr_ain[13];
 
 // The a10 VRAM address line. (Used for mirroring)
 reg vram_a10_t;
-always begin
+always @* begin
 	case({onescreen, mirroring})
 		2'b00: vram_a10_t = chr_ain[11];   // One screen, horizontal
 		2'b01: vram_a10_t = chr_ain[10];   // One screen, vertical
@@ -784,7 +784,7 @@ end else if (ce) begin
 	end
 end
 
-always begin
+always @* begin
 	// mirroring mode
 	casez({mapper89,flags[14]})
 		2'b00   :   vram_a10 = {chr_ain[11]};    // horizontal
@@ -897,6 +897,7 @@ module Mapper28(
 	input        prg_write,   // prg write
 	input  [7:0] prg_din,     // prg data in
 	inout  [7:0] prg_dout_b,  // prg data out
+	output       prg_allow,
 	inout        prg_allow_b, // Enable access to memory for the specified operation.
 	input [13:0] chr_ain,     // chr address in
 	inout [21:0] chr_aout_b,  // chr address out
@@ -1016,7 +1017,7 @@ end else if (ce) begin
 	end
 end
 
-always begin
+always @* begin
 	// mirroring mode
 	casez(mode[1:0])
 		2'b0? : vram_a10 = {mode[0]};        // 1 screen lower

src/mappers/iir_filter.v

@@ -67,6 +67,10 @@ wire [39:0] x = inp_mul[59:20];
 wire [39:0] y = x + tap0;
 
 wire [39:0] tap0;
+wire [39:0] tap1;
+wire [39:0] tap2;
+reg        ch = 0;
+
 iir_filter_tap iir_tap_0
 (
 	.clk(clk),
@@ -81,7 +85,6 @@ iir_filter_tap iir_tap_0
 	.tap(tap0)
 );
 
-wire [39:0] tap1;
 iir_filter_tap iir_tap_1
 (
 	.clk(clk),
@@ -96,7 +99,6 @@ iir_filter_tap iir_tap_1
 	.tap(tap1)
 );
 
-wire [39:0] tap2;
 iir_filter_tap iir_tap_2
 (
 	.clk(clk),
@@ -113,7 +115,6 @@ iir_filter_tap iir_tap_2
 
 wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20];
 
-reg        ch = 0;
 reg [15:0] out_l, out_r, out_m;
 reg [15:0] inp, inp_m;
 always @(posedge clk) if (ce) begin