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Analog fixes #76

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wants to merge 121 commits into from
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Analog fixes #76

wants to merge 121 commits into from

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jpc-lip6
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Fixes needed after the switch to meson, as the analog designs are not part of the regression test, they where broken...

robtaylor
robtaylor previously approved these changes Oct 25, 2023
Comment on lines +569 to +574
path = None
for pathVar in [ 'PATH', 'path' ]:
if pathVar in os.environ:
path = os.environ[ pathVar ]
os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix()
break
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Oh, does this add a dependency on alliance?

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No, it doesn't. This file is part of designflow which is my overlay over doit to ease the creation of Makefile
replacement specially targeted for EDA. It provides support for Yosys, KLayout, SV2V, Alliance, ...

So this particular piece of code just try to locate Alliance if it can find it. If it doesn't, that's non-blocking,
you will just not be able to use it.

In a way, it may be setup as a separate tool. But:

  1. I wouldn't like to multiply too much the number of repositories (and/or packages).
  2. And now that cgt is not there anymore, you can only start Coriolis through a default dodo.py file, which
    we may supply a default one for each technology. That is an aspect to be taken into account for the technology
    packages.

@robtaylor robtaylor dismissed their stale review October 25, 2023 22:11

not approved! if alliance is a dependency, then we need to do more..

lanserge and others added 24 commits January 16, 2024 20:44
CRL.Verilog.save(cell, 0) -> exports cell into Verilog netlist file

Co-authored-by: Serge Rabyking <[email protected]>
…export Verilog netlist. (#84)

Co-authored-by: Serge Rabyking <[email protected]>
* Restrict the RoutingPad boxes to the cell abutment box.
* Check that there are overlaping bounds returned by Tracks::getOverlapBounds().
* Pass the current net to Track::getFreeInterval(), so it is not considered
  a blockage...
* Returns the set of biggest rectangles inscribed inside the Rectilinear.
  This is *not* a partition, the rectangles overlaps. This is intended for
  the router to select the biggest rectangle in the direction he sees fit
  and making it a RoutingPad.
* In AnabaticEngine::loadGlobalRouting(), call relaxOverConstraineds()
  only if M1 is vertical (may write another one for M1 horizontal).
* In AnabaticEngine::computeEdgeCapacities(), don't complain for
  offgrid M1 if it is allowed...
* In AutoContactTerminal::updateGeometry(), implement dragging on
  horizontal M1.
* In AutoSegment::getExtensionCap(), manage the case when neither
  source nor target is requested. Return the bottom layer cap in
  that instance (for M1 terminals).
* In AutoVertical::updatePositions(), on non-preferred segments,
  the extention must be further extendend as to include perpendiculars
  axis of tracks that we may impact.
* In AutoHorizontal::updatePositions(), idem.
* In Configuration::selectRpComponent(), detect M1 offgrid components
  and flag them. HSmall & VSmall are now forced to be flagged as
  *punctual*.
* In NetBuilderHV, support for M1 offgrid terminals. Systematically
  use doRp_Accesss() and never call directly doRp_AutoContacts().
* In NetBuilderVH, general overhaul & bug fixes.
* In RoutingPad, add a flag to tell that a component has been selected.
* In RoutingPlane::getTrackByPosition(), add failsafe when we are
  before the first track axis or after the last.
@jpc-lip6 jpc-lip6 marked this pull request as ready for review January 16, 2024 19:52
@jpc-lip6 jpc-lip6 closed this Jan 22, 2024
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Merge through rebase-analog-fixes

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6 participants