ym3438: add ym2612 status emulation option

nukeykt · Aug 21, 2023 · a1d5c69 · a1d5c69
1 parent 4cc0bf7
commit a1d5c69
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Showing 4 changed files with 33 additions and 11 deletions.
diff --git a/fc1004.v b/fc1004.v
@@ -203,7 +203,8 @@ module fc1004
 	input tmss_enable,
 	input [15:0] tmss_data,
 	output [9:0] tmss_address,
-	output vdp_hsync2
+	output vdp_hsync2,
+	input ym2612_status_enable
 	);
 
 	wire vdp_ys; // w1009
@@ -391,7 +392,8 @@ module fc1004
 		.MOL_2612(MOL_2612),
 		.MOR_2612(MOR_2612),
 		.fm_clk1(fm_clk1),
-		.DAC_ch_index(DAC_ch_index)
+		.DAC_ch_index(DAC_ch_index),
+		.ym2612_status_enable(ym2612_status_enable)
 		);
 
 

diff --git a/md_board.v b/md_board.v
@@ -109,7 +109,8 @@ module md_board
 	output vdp_lcb,
 	output vdp_psg_clk1,
 	output fm_clk1,
-	output vdp_hsync2
+	output vdp_hsync2,
+	input ym2612_status_enable
 
 	);
 
@@ -461,7 +462,8 @@ module md_board
 		.tmss_enable(tmss_enable),
 		.tmss_data(tmss_data),
 		.tmss_address(tmss_address),
-		.vdp_hsync2(vdp_hsync2)
+		.vdp_hsync2(vdp_hsync2),
+		.ym2612_status_enable(ym2612_status_enable)
 		);
 
 	assign fm_sel23 = TEST0_o;

diff --git a/ym3438.v b/ym3438.v
@@ -40,7 +40,8 @@ module ym3438(
 	//output d_c2,
 	output [9:0] MOL_2612, MOR_2612,
 	output fm_clk1,
-	output [2:0] DAC_ch_index
+	output [2:0] DAC_ch_index,
+	input ym2612_status_enable
 	);
 
 	wire c1, c2;
@@ -146,7 +147,8 @@ module ym3438(
 		.bank(bank),
 		.data_o(DATA_o),
 		.io_dir(DATA_o_z),
-		.irq(IRQ)
+		.irq(IRQ),
+		.ym2612_status_enable(ym2612_status_enable)
 		);
 
 	wire [3:0] reg_lfo;

diff --git a/ym3438_io.v b/ym3438_io.v
@@ -24,11 +24,12 @@ module ym3438_io
 	output bank,
 	output [7:0] data_o,
 	output io_dir,
-	output irq
+	output irq,
+	input ym2612_status_enable
 	);
 
 
-	wire read_en = ~RD & IC & ~CS;
+	wire read_en = (~RD & IC & ~CS) & (~ym2612_status_enable | address == 2'h0);
 	wire write_addr = (~WR & ~CS & ~address[0]) | ~IC;
 	wire write_data = ~WR & ~CS & address[0] & IC;
 
@@ -198,9 +199,24 @@ module ym3438_io
 		.nval(timer_b_status_sl_out)
 		);
 
-	assign data_o =
-		(read_status ? { ~busy_state_o, 5'h0, timer_b_status_sl_out, timer_a_status_sl_out } : 8'h0) |
-		(read_debug ? debug_data : 8'h0);
+	reg [7:0] data_o_r;
+	reg [25:0] status_time;
+
+	always @(posedge MCLK)
+	begin
+		if (read_status)
+			data_o_r <= { ~busy_state_o, 5'h0, timer_b_status_sl_out, timer_a_status_sl_out };
+		if (read_debug)
+			data_o_r <= debug_data;
+
+		if (read_status | read_debug)
+			status_time <= 26'd40000000;
+		else if (status_time)
+			status_time <= status_time - 1;
+		else
+			data_o_r <= 8'h0;
+	end
+	assign data_o = data_o_r;
 
 	assign irq = ~(timer_a_status_sl_out | timer_b_status_sl_out);