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Merge pull request #36 from os-fpga/fail_sim_1.1.1_internal
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Fail sim 1.1.1 internal
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@moinijaz
moinijaz authored Mar 27, 2024
2 parents 9257760 + 7cb30d5 commit 92e2cea
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153 changes: 78 additions & 75 deletions blackbox_models/cell_sim_blackbox.v
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Original file line number Diff line number Diff line change
Expand Up @@ -170,13 +170,13 @@ endmodule
`celldefine
(* blackbox *)
module FIFO18KX2 #(
parameter DATA_WRITE_WIDTH1 = 18, // FIFO data write width, FIFO 1 (1-18)
parameter DATA_READ_WIDTH1 = 18, // FIFO data read width, FIFO 1 (1-18)
parameter DATA_WRITE_WIDTH1 = 18, // FIFO data write width, FIFO 1 (9, 18)
parameter DATA_READ_WIDTH1 = 18, // FIFO data read width, FIFO 1 (9, 18)
parameter FIFO_TYPE1 = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer, FIFO 1 (SYNCHRONOUS/ASYNCHRONOUS)
parameter [10:0] PROG_EMPTY_THRESH1 = 11'h004, // 11-bit Programmable empty depth, FIFO 1
parameter [10:0] PROG_FULL_THRESH1 = 11'h7fa, // 11-bit Programmable full depth, FIFO 1
parameter DATA_WRITE_WIDTH2 = 18, // FIFO data write width, FIFO 2 (1-18)
parameter DATA_READ_WIDTH2 = 18, // FIFO data read width, FIFO 2 (1-18)
parameter DATA_WRITE_WIDTH2 = 18, // FIFO data write width, FIFO 2 (9, 18)
parameter DATA_READ_WIDTH2 = 18, // FIFO data read width, FIFO 2 (9, 18)
parameter FIFO_TYPE2 = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer, FIFO 2 (SYNCHRONOUS/ASYNCHRONOUS)
parameter [10:0] PROG_EMPTY_THRESH2 = 11'h004, // 11-bit Programmable empty depth, FIFO 2
parameter [10:0] PROG_FULL_THRESH2 = 11'h7fa // 11-bit Programmable full depth, FIFO 2
Expand Down Expand Up @@ -227,8 +227,8 @@ endmodule
`celldefine
(* blackbox *)
module FIFO36K #(
parameter DATA_WRITE_WIDTH = 36, // FIFO data write width (1-36)
parameter DATA_READ_WIDTH = 36, // FIFO data read width (1-36)
parameter DATA_WRITE_WIDTH = 36, // FIFO data write width (9, 18, 36)
parameter DATA_READ_WIDTH = 36, // FIFO data read width (9, 18, 36)
parameter FIFO_TYPE = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer (SYNCHRONOUS/ASYNCHRONOUS)
parameter [11:0] PROG_EMPTY_THRESH = 12'h004, // 12-bit Programmable empty depth
parameter [11:0] PROG_FULL_THRESH = 12'hffa // 12-bit Programmable full depth
Expand All @@ -254,44 +254,45 @@ module FIFO36K #(
endmodule
`endcelldefine
//
// I_BUF black box model
// Input buffer
// I_BUF_DS black box model
// input differential buffer
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module I_BUF #(
module I_BUF_DS #(
parameter WEAK_KEEPER = "NONE" // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN)
`ifdef RAPIDSILICON_INTERNAL
, parameter IOSTANDARD = "DEFAULT" // IO Standard
, parameter IOSTANDARD = "DEFAULT", // IO Standard
parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
`endif // RAPIDSILICON_INTERNAL
) (
input logic I,
input logic I_P,
input logic I_N,
input logic EN,
output logic O
output reg O
);
endmodule
`endcelldefine
//
// I_BUF_DS black box model
// input differential buffer
// I_BUF black box model
// Input buffer
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module I_BUF_DS #(
module I_BUF #(
parameter WEAK_KEEPER = "NONE" // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN)
`ifdef RAPIDSILICON_INTERNAL
, parameter IOSTANDARD = "DEFAULT", // IO Standard
parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
, parameter IOSTANDARD = "DEFAULT" // IO Standard
`endif // RAPIDSILICON_INTERNAL
) (
input logic I_P,
input logic I_N,
(* iopad_external_pin *)
input logic I,
input logic EN,
output reg O
output logic O
);
endmodule
`endcelldefine
Expand Down Expand Up @@ -458,90 +459,92 @@ module LUT6 #(
endmodule
`endcelldefine
//
// O_BUF black box model
// Output buffer
// O_BUF_DS black box model
// Output differential buffer
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module O_BUF
module O_BUF_DS
`ifdef RAPIDSILICON_INTERNAL
#(
parameter IOSTANDARD = "DEFAULT", // IO Standard
parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
)
`endif // RAPIDSILICON_INTERNAL
(
input logic I,
output logic O
output logic O_P,
output logic O_N
);
endmodule
`endcelldefine
//
// O_BUFT black box model
// Output tri-state buffer
// O_BUFT_DS black box model
// Output differential tri-state buffer
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module O_BUFT #(
module O_BUFT_DS #(
parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN)
`ifdef RAPIDSILICON_INTERNAL
, parameter IOSTANDARD = "DEFAULT", // IO Standard
parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
`endif // RAPIDSILICON_INTERNAL
) (
input logic I,
input logic T,
output logic O
output logic O_P,
output logic O_N
);
endmodule
`endcelldefine
//
// O_BUFT_DS black box model
// Output differential tri-state buffer
// O_BUFT black box model
// Output tri-state buffer
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module O_BUFT_DS #(
module O_BUFT #(
parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN)
`ifdef RAPIDSILICON_INTERNAL
, parameter IOSTANDARD = "DEFAULT", // IO Standard
parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
`endif // RAPIDSILICON_INTERNAL
) (
input logic I,
input logic T,
output logic O_P,
output logic O_N
(* iopad_external_pin *)
output logic O
);
endmodule
`endcelldefine
//
// O_BUF_DS black box model
// Output differential buffer
// O_BUF black box model
// Output buffer
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module O_BUF_DS
module O_BUF
`ifdef RAPIDSILICON_INTERNAL
#(
parameter IOSTANDARD = "DEFAULT", // IO Standard
parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
)
`endif // RAPIDSILICON_INTERNAL
(
input logic I,
output logic O_P,
output logic O_N
(* iopad_external_pin *)
output logic O
);
endmodule
`endcelldefine
Expand Down Expand Up @@ -584,45 +587,45 @@ module O_DELAY #(
endmodule
`endcelldefine
//
// O_SERDES black box model
// Output Serializer
// O_SERDES_CLK black box model
// Output Serializer Clock
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module O_SERDES #(
module O_SERDES_CLK #(
parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR)
parameter WIDTH = 4 // Width of input data to serializer (3-10)
parameter CLOCK_PHASE = 0 // Clock phase (0,90,180,270)
) (
input logic [WIDTH-1:0] D,
input logic RST,
input logic LOAD_WORD,
input logic CLK_IN,
input logic OE_IN,
output logic OE_OUT,
output logic Q,
input logic CHANNEL_BOND_SYNC_IN,
output logic CHANNEL_BOND_SYNC_OUT,
input logic CLK_EN,
output reg OUTPUT_CLK,
input logic PLL_LOCK,
input logic PLL_CLK
);
endmodule
`endcelldefine
//
// O_SERDES_CLK black box model
// Output Serializer Clock
// O_SERDES black box model
// Output Serializer
//
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
//
`celldefine
(* blackbox *)
module O_SERDES_CLK #(
module O_SERDES #(
parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR)
parameter CLOCK_PHASE = 0 // Clock phase (0,90,180,270)
parameter WIDTH = 4 // Width of input data to serializer (3-10)
) (
input logic CLK_EN,
output reg OUTPUT_CLK,
input logic [WIDTH-1:0] D,
input logic RST,
input logic LOAD_WORD,
input logic CLK_IN,
input logic OE_IN,
output logic OE_OUT,
output logic Q,
input logic CHANNEL_BOND_SYNC_IN,
output logic CHANNEL_BOND_SYNC_OUT,
input logic PLL_LOCK,
input logic PLL_CLK
);
Expand Down Expand Up @@ -881,16 +884,16 @@ endmodule
module TDP_RAM18KX2 #(
parameter [16383:0] INIT1 = {16384{1'b0}}, // Initial Contents of data memory, RAM 1
parameter [2047:0] INIT1_PARITY = {2048{1'b0}}, // Initial Contents of parity memory, RAM 1
parameter WRITE_WIDTH_A1 = 18, // Write data width on port A, RAM 1 (1-18)
parameter WRITE_WIDTH_B1 = 18, // Write data width on port B, RAM 1 (1-18)
parameter READ_WIDTH_A1 = 18, // Read data width on port A, RAM 1 (1-18)
parameter READ_WIDTH_B1 = 18, // Read data width on port B, RAM 1 (1-18)
parameter WRITE_WIDTH_A1 = 18, // Write data width on port A, RAM 1 (1, 2, 4, 9, 18)
parameter WRITE_WIDTH_B1 = 18, // Write data width on port B, RAM 1 (1, 2, 4, 9, 18)
parameter READ_WIDTH_A1 = 18, // Read data width on port A, RAM 1 (1, 2, 4, 9, 18)
parameter READ_WIDTH_B1 = 18, // Read data width on port B, RAM 1 (1, 2, 4, 9, 18)
parameter [16383:0] INIT2 = {16384{1'b0}}, // Initial Contents of memory, RAM 2
parameter [2047:0] INIT2_PARITY = {2048{1'b0}}, // Initial Contents of memory, RAM 2
parameter WRITE_WIDTH_A2 = 18, // Write data width on port A, RAM 2 (1-18)
parameter WRITE_WIDTH_B2 = 18, // Write data width on port B, RAM 2 (1-18)
parameter READ_WIDTH_A2 = 18, // Read data width on port A, RAM 2 (1-18)
parameter READ_WIDTH_B2 = 18 // Read data width on port B, RAM 2 (1-18)
parameter WRITE_WIDTH_A2 = 18, // Write data width on port A, RAM 2 (1, 2, 4, 9, 18)
parameter WRITE_WIDTH_B2 = 18, // Write data width on port B, RAM 2 (1, 2, 4, 9, 18)
parameter READ_WIDTH_A2 = 18, // Read data width on port A, RAM 2 (1, 2, 4, 9, 18)
parameter READ_WIDTH_B2 = 18 // Read data width on port B, RAM 2 (1, 2, 4, 9, 18)
) (
input logic WEN_A1,
input logic WEN_B1,
Expand Down Expand Up @@ -944,10 +947,10 @@ endmodule
module TDP_RAM36K #(
parameter [32767:0] INIT = {32768{1'b0}}, // Initial Contents of memory
parameter [4095:0] INIT_PARITY = {4096{1'b0}}, // Initial Contents of memory
parameter WRITE_WIDTH_A = 36, // Write data width on port A (1-36)
parameter READ_WIDTH_A = WRITE_WIDTH_A, // Read data width on port A (1-36)
parameter WRITE_WIDTH_B = WRITE_WIDTH_A, // Write data width on port B (1-36)
parameter READ_WIDTH_B = READ_WIDTH_A // Read data width on port B (1-36)
parameter WRITE_WIDTH_A = 36, // Write data width on port A (1, 2, 4, 9, 18, 36)
parameter READ_WIDTH_A = WRITE_WIDTH_A, // Read data width on port A (1, 2, 4, 9, 18, 36)
parameter WRITE_WIDTH_B = WRITE_WIDTH_A, // Write data width on port B (1, 2, 4, 9, 18, 36)
parameter READ_WIDTH_B = READ_WIDTH_A // Read data width on port B (1, 2, 4, 9, 18, 36)
) (
input logic WEN_A,
input logic WEN_B,
Expand Down
12 changes: 6 additions & 6 deletions sim_models_internal/verilog/tb/PLL_tb.v
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Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
`timescale 1ps/1ps
`timescale 1fs/1fs

module PLL_tb;

// Parameters
localparam DIVIDE_CLK_IN_BY_2 = "TRUE";
localparam DIVIDE_CLK_IN_BY_2 = "FALSE";
localparam PLL_MULT = 80;
localparam PLL_DIV = 2;
localparam PLL_POST_DIV = 2;

real CLK_PERIOD = 25000; // 25000ps =25ns = 40MHz
real CLK_PERIOD = 25000000; // 40MHz

//Ports
reg PLL_EN;
Expand Down Expand Up @@ -70,11 +70,11 @@ begin
expected_period=(CLK_PERIOD*PLL_DIV*PLL_POST_DIV*CLK_DIV)/PLL_MULT;

#1;
// passing is if less than 10ps difference in period
// passing is if less than 10fs difference in period
if( $abs(clk_out_period-expected_period) < 10)
$display("CLOCK OUT TEST PASSED [less than 10ps difference] (actual / expected): %0d ps / %0d ps", clk_out_period, expected_period);
$display("CLOCK OUT TEST PASSED [less than 10fs difference] (actual / expected): %0d fs / %0d fs", clk_out_period, expected_period);
else begin
$display("CLOCK OUT TEST FAILED [more than 10ps difference] (actual / expected): %0d ps / %0d ps", clk_out_period, expected_period);
$display("CLOCK OUT TEST FAILED [more than 10fs difference] (actual / expected): %0d fs / %0d fs", clk_out_period, expected_period);
end

fork
Expand Down
8 changes: 4 additions & 4 deletions specs_internal/FIFO18KX2.yaml
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Expand Up @@ -177,12 +177,12 @@ ports:

parameters:
DATA_WRITE_WIDTH1:
desc: FIFO data write width, FIFO 1 (1-18)
desc: FIFO data write width, FIFO 1 (9, 18)
type: integer
default: 18
range: 1 .. 18
DATA_READ_WIDTH1:
desc: FIFO data read width, FIFO 1 (1-18)
desc: FIFO data read width, FIFO 1 (9, 18)
type: integer
default: 18
range: 1 .. 18
Expand All @@ -201,12 +201,12 @@ parameters:
default: 11'h7fa
vector: 11
DATA_WRITE_WIDTH2:
desc: FIFO data write width, FIFO 2 (1-18)
desc: FIFO data write width, FIFO 2 (9, 18)
type: integer
default: 18
range: 1 .. 18
DATA_READ_WIDTH2:
desc: FIFO data read width, FIFO 2 (1-18)
desc: FIFO data read width, FIFO 2 (9, 18)
type: integer
default: 18
range: 1 .. 18
Expand Down
4 changes: 2 additions & 2 deletions specs_internal/FIFO36K.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -114,12 +114,12 @@ ports:

parameters:
DATA_WRITE_WIDTH:
desc: FIFO data write width (1-36)
desc: FIFO data write width (9, 18, 36)
type: integer
default: 36
range: 1 .. 36
DATA_READ_WIDTH:
desc: FIFO data read width (1-36)
desc: FIFO data read width (9, 18, 36)
type: integer
default: 36
range: 1 .. 36
Expand Down
1 change: 1 addition & 0 deletions specs_internal/I_BUF.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ ports:
I:
dir: input
desc: Data input (connect to top-level port)
bb_attributes: iopad_external_pin
EN:
dir: input
desc: Enable the input
Expand Down
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