Skip to content

Commit

Permalink
Updated IPs with path fixes
Browse files Browse the repository at this point in the history
  • Loading branch information
bilal458 committed Dec 6, 2024
1 parent 5e292a2 commit a2ad49f
Show file tree
Hide file tree
Showing 5 changed files with 8 additions and 13 deletions.
3 changes: 1 addition & 2 deletions rapidsilicon/ip/axi_fifo/v1_0/sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,7 @@ Raptor_PATH := $(shell dirname $(shell which raptor ))
FOLDER_PATH = ./../../../../../../../../../ # /path/to/project

# Dynamically fetch the name of the folder (first one in this case)
FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type d -name "project*" | xargs -n 1 basename | head -n 1)

FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type f -name "*.ospr" | xargs -n 1 basename | sed 's/\.ospr$$//' | head -n 1)
#@echo "The folder name is: $(FOLDER_NAME)"

ifeq ($(POST_SYNTH_SIM), 0)
Expand Down
3 changes: 1 addition & 2 deletions rapidsilicon/ip/axi_ram/v1_0/sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,7 @@ Raptor_PATH := $(shell dirname $(shell which raptor ))
FOLDER_PATH = ./../../../../../../../../../ # /path/to/project

# Dynamically fetch the name of the folder (first one in this case)
FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type d -name "project*" | xargs -n 1 basename | head -n 1)

FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type f -name "*.ospr" | xargs -n 1 basename | sed 's/\.ospr$$//' | head -n 1)
#@echo "The folder name is: $(FOLDER_NAME)"

ifeq ($(POST_SYNTH_SIM), 0)
Expand Down
3 changes: 1 addition & 2 deletions rapidsilicon/ip/axi_register/v1_0/sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,7 @@ Raptor_PATH := $(shell dirname $(shell which raptor ))
FOLDER_PATH = ./../../../../../../../../../ # /path/to/project

# Dynamically fetch the name of the folder (first one in this case)
FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type d -name "project*" | xargs -n 1 basename | head -n 1)

FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type f -name "*.ospr" | xargs -n 1 basename | sed 's/\.ospr$$//' | head -n 1)
#@echo "The folder name is: $(FOLDER_NAME)"

ifeq ($(POST_SYNTH_SIM), 0)
Expand Down
5 changes: 2 additions & 3 deletions rapidsilicon/ip/axis_ram_switch/v1_0/sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -44,12 +44,11 @@ Raptor_PATH := $(shell dirname $(shell which raptor ))
FOLDER_PATH = ./../../../../../../../../../ # /path/to/project

# Dynamically fetch the name of the folder (first one in this case)
FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type d -name "project*" | xargs -n 1 basename | head -n 1)

FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type f -name "*.ospr" | xargs -n 1 basename | sed 's/\.ospr$$//' | head -n 1)
#@echo "The folder name is: $(FOLDER_NAME)"

ifeq ($(POST_SYNTH_SIM), 0)
VERILOG_SOURCES += ./../src*.v
VERILOG_SOURCES += ./../src/*.v
else ifeq ($(POST_SYNTH_SIM), 1)
VERILOG_SOURCES += $(Raptor_PATH)/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/*.v
VERILOG_SOURCES += ./../../../../../../../synth_1_1/synthesis/$(FOLDER_NAME)_post_synth.v
Expand Down
7 changes: 3 additions & 4 deletions rapidsilicon/ip/axis_switch/v1_0/sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@
# THE SOFTWARE.

TOPLEVEL_LANG = verilog

SIM ?= icarus
WAVES ?= 1

Expand All @@ -44,12 +44,11 @@ Raptor_PATH := $(shell dirname $(shell which raptor ))
FOLDER_PATH = ./../../../../../../../../../ # /path/to/project

# Dynamically fetch the name of the folder (first one in this case)
FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type d -name "project*" | xargs -n 1 basename | head -n 1)

FOLDER_NAME = $(shell find $(FOLDER_PATH) -maxdepth 1 -type f -name "*.ospr" | xargs -n 1 basename | sed 's/\.ospr$$//' | head -n 1)
#@echo "The folder name is: $(FOLDER_NAME)"

ifeq ($(POST_SYNTH_SIM), 0)
VERILOG_SOURCES += ./../src*.v
VERILOG_SOURCES += ./../src/*.v
else ifeq ($(POST_SYNTH_SIM), 1)
VERILOG_SOURCES += $(Raptor_PATH)/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/*.v
VERILOG_SOURCES += ./../../../../../../../synth_1_1/synthesis/$(FOLDER_NAME)_post_synth.v
Expand Down

0 comments on commit a2ad49f

Please sign in to comment.